Andrew Touma

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  1. Thank you very much for the assistance! I was able to make the necessary corrections and my project is running smoothly now. I also found some other errors in the logic of my code, which I have corrected as well.
  2. The rest of my .xdc file is comments from the other constraints I am not using. For my main design, I have three design sources with one being the top level. 1st (Top Level): module brain(input wire clk, output wire [1:0]o1, output wire [1:0]o2, output wire [1:0]o3, output wire [1:0]o4); wire new_clk; main main_unit(.clk(clk), .out(new_clk)); logic logic_unit(.clk(new_clk), .o1(o1), .o2(o2), .o3(o3), .o4(o4)); endmodule 2nd: `timescale 1ns / 1ps module main(input wire clk,output wire out); reg [18:0] r_reg; wire [18:0] r_next; always @ (posedge clk) r_reg <= r_next; assign r_next = (r_reg == 500) ? 0 : r_reg +1; assign out = ( r_reg == 500) ?1'b1 : 1'b0; endmodule 3rd: module logic( input wire clk, output reg[1:0] o1, output reg[1:0] o2, output reg[1:0] o3, output reg[1:0] o4 ); reg[18:0] count = 1; reg x1 = 1; reg x2 = 1; reg x3 = 1; reg x4 = 1; [email protected](posedge clk) begin if (count == 1) begin x2 <= 0; x3 <= 0; x4 <= 0; end if (count == 2) begin x3 <= 0; x4 <= 0; end if (count == 3) begin x4 <= 0; end o1 <= x1; o2 <= x2; o3 <= x3; o4 <= x4; count = count + 1; end endmodule
  3. Hello, I am a fairly new to using the Basys 3 and a student using it for a project. I am attempting to output 4 separate variables from the Pmod ports on the board using the JA Pmod part. When I run synthesis, implementation, and then bitstream, I get the same error for all but one of my outputs. My error message: [Common 17-69] Command failed: Site cannot be assigned to more than one port ["D:/LogicLab/SignalsProjectMK1/SignalsProjectMK1.srcs/constrs_1/new/BasysOut.xdc":16] Constraint: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ##Pmod Header JA ##Sch name = JA1 set_property PACKAGE_PIN J1 [get_ports {o1}] set_property IOSTANDARD LVCMOS33 [get_ports {o1}] ##Sch name = JA2 set_property PACKAGE_PIN L2 [get_ports {o2}] set_property IOSTANDARD LVCMOS33 [get_ports {o2}] ##Sch name = JA3 set_property PACKAGE_PIN J2 [get_ports {o3}] set_property IOSTANDARD LVCMOS33 [get_ports {o3}] ##Sch name = JA4 set_property PACKAGE_PIN G2 [get_ports {o4}] set_property IOSTANDARD LVCMOS33 [get_ports {o4}] (o1-o4 are my 4 variables I want to output) Is my constraint file the cause of this error, and if so, how do I go about correcting my mistake? Thank you for the assistance.