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  1. tomii


    Thanks for the welcome and the advice. I grabbed the Zynq board, as we'll probably be using them at work on a project soon, so I figured it was time I took it for a spin. I've made it most of the way through "The Zynq Book" and its tutorials (I've not actually pushed them into HW, yet).. I'm trying to interface a couple of PMODs to one of my Opal Kelly boards right now, and it's giving me fits. I swear I kind of recall seeing this problem once upon a time, but can't for the life of me figure it out - and my Google foo is no bueno on it. Regardless, I'm sure I'll eventually work it out
  2. Okay, just to be sure, I've done 3 things: 1) Moved to a different set of IO pins, and forced them to LVCMOS33 2) I've slowed down CS "up" time to ensure it makes it to 3.3V 3) I've slowed the SCK to about 4MHz 4) I've verified the drive input to the DAC All results in the same problem. Yes, I realize that maybe CS is going low too late compared to SCK, but when I unload the output pins, they still do the same thing as before - they come alive and properly put out 3.3V data. So, maybe the data is skewed by an SCK cycle, but the question
  3. Looks like you're correct about the missing falling edge - But that's secondary for now, as I can't seem to read any data back. - Yes, the AD1 outputs run through a schmitt triggers and a 100 Ohm resistor before landing on pins. This is partly why they are not managing to go high, I think - it appears the FPGA might be pulling the inputs low. And therein lies the rub - I've moved the pins around to different connectors, and end up with the same results, and it's maddening (for the moment). I am beginning to believe that there's configuration issue with the FPGA, and I need to fig
  4. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Ras
  5. tomii


    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting