tomii

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  1. tomii

    Howdy

    Thanks for the welcome and the advice. I grabbed the Zynq board, as we'll probably be using them at work on a project soon, so I figured it was time I took it for a spin. I've made it most of the way through "The Zynq Book" and its tutorials (I've not actually pushed them into HW, yet).. I'm trying to interface a couple of PMODs to one of my Opal Kelly boards right now, and it's giving me fits. I swear I kind of recall seeing this problem once upon a time, but can't for the life of me figure it out - and my Google foo is no bueno on it. Regardless, I'm sure I'll eventually work it out, hopefully sooner rather than later I looked in to those SYZYGY boards... I liked what I saw, but the price point on those bad boys... Too much for my wallet for now!
  2. Okay, just to be sure, I've done 3 things: 1) Moved to a different set of IO pins, and forced them to LVCMOS33 2) I've slowed down CS "up" time to ensure it makes it to 3.3V 3) I've slowed the SCK to about 4MHz 4) I've verified the drive input to the DAC All results in the same problem. Yes, I realize that maybe CS is going low too late compared to SCK, but when I unload the output pins, they still do the same thing as before - they come alive and properly put out 3.3V data. So, maybe the data is skewed by an SCK cycle, but the question still remains: "what is causing the loading of the inputs - why are they acting like outputs?
  3. Looks like you're correct about the missing falling edge - But that's secondary for now, as I can't seem to read any data back. - Yes, the AD1 outputs run through a schmitt triggers and a 100 Ohm resistor before landing on pins. This is partly why they are not managing to go high, I think - it appears the FPGA might be pulling the inputs low. And therein lies the rub - I've moved the pins around to different connectors, and end up with the same results, and it's maddening (for the moment). I am beginning to believe that there's configuration issue with the FPGA, and I need to figure out the overloading of the AD1 outputs before I can really move any further along (I think). In the end this will probably be something stupidly simple that I'm overlooking (or maybe a funky ground loop). Any ideas for Spartan3E config?
  4. Hey all, First off, I apologize - I'm at work, now, with no access to the hardware, o-scope, etc. So all from memory for now, until I can get some time at home.... NOTE: All development being done under Xilinx ISE 14.7 WebPack. Target platform is an Opal Kelly XEM3005 (Xilinx Spartan 3E) Day 1: Wrote & sim'd Verilog to drive a PMODAD1 12b ADC. Seemed to work as planned. Day 2: Tried interfacing to an Opal Kelly XEM3005 (Spartan 3E) board with 3.3V logic & power. No joy. Funky stuff going on. Began troubleshooting. Day 3: Wrote code for Raspberry Pi Zero W (using WiringPi) to drive the AD1. Everything works as it should. Data reads work as close to perfect as I can ask for. Day 4: Continue troubleshooting FPGA - realize my constraints file is no bueno, and is assigning FPGA pins incorrectly. Fixed that. (So, reasonably sure that constraints file is copacetic) Day 5: Wrote code to drive a PMOD DA2 2-channel 12b DAC. Code Sim'd. Works well. Integrated into FPGA - code works well, DA2 works as advertised. Also works well with OK's FrontPanel - I can give a command from the PC, and the DA2 spits out the appropriate voltage. (This was another step to validate FPGA platform functionality & correctness). Day 6: Re-code and re-sim DA1 Verilog. Works as expected. Day 7: Integrate code onto XEM3005 - still no joy. Probe with oscilloscope: Power good - 3.3V, rock solid Ground good: little to no noise. Chip Select (CS) looks good - ~990kHz rate, normally high, Goes low for readout periods. Less than perfect due to being on a protoboard connected via a 6: cable. Serial clock (SCK) looks good - ~16MHz, only active during CS Low periods, high when CS is high (quiet time) DO and D1 outputs - constant low. A fair amount of digital noise. Sometimes, having a probe attached to D0 or D1 with the other probe attached to SCK or CS will couple noise in to the FPGA, giving me a noisy signal that is meaningless (except for the fact that it tells me my inputs are working - or so I think) It appears as though (bare with me - I'm an analog guy) the lines are heavily loaded - i.e., something is pulling the lines to ground. I see on the AD1 datasheet that the outputs are protected by 100 Ohm resistors, so this seems a potential (likely?) culprit (?) Not instantiating IOB's in my code, but those normally aren't necessary except to override defaults in the constraints file. Double- and triple-checked that the D0 and D1 ports are set up as inputs. Constraints file does not explicitly turn on Pull-ups or pull-downs. (LOGIC_3v3, IIRC) Recoded main fixture to move connections to different pins. No change in results - everything (appears) identical. Day 8: Just got home - did some double checking and disconnected the PMOD outputs from the FPGA: With the FPGA disconnected, the signals look pretty darned good: Took some quick measurements of the FPGA input pins - they seem to hava a constant ~0.75V on them with quite a bit of digital trash... This is clearly (I think) an FPGA setup problem.. So, here I am... Looking for clues. Anyone have any? Thanks in advance
  5. tomii

    Howdy

    Hey everybody! Taught myself just enough Verilog to be dangerous from 2013-2015 or so. Wrote a bunch of (boring) articles for a now-defunct trade site (absorbed into EETimes) about the process. Some of that stuff might still be available if you're lucky enough to find it. Did most of my learning on Opal Kelly XEM3005 - which I gotta say is an *excellent* platform (get yourself a breakout board, tho). I've started doing some stuff with Digilent devices a couple years ago, but haven't had any real opportunity to dig in to the "new" Arty or Zynq-based boards. So sitting around my home "lab," I've got a few Opal Kelly boards (XEM3001, XEM3005, and a couple others) - I love the FrontPanel system they've developed. I've also got an Arty (35T) and now a Cora (low-end Zedboard), and I'm itching to learn some stuff there. I also do a fair amount of bare-metal embedded when I need to (e.g. Atmel/Microchip microcontrollers), and have also recently been doing some stuff with embedded Linux on the pi platform. Lastly, let's talk about the registration process. Jimminy Christmas, it took me and another engineer 8 tries to get validated! Holy cow, am I st00pid, or what? -Tom