Guru Prasanth S

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Everything posted by Guru Prasanth S

  1. Up to now all is well. If any issue i will post. Once again Thanks for your support.
  2. Hi, I removed debug ILA in the project and generated bit file. It is perfectly working for HDMI source as PC output . Thanks for your cooperation. Thanks, Guru
  3. Hi, Now i am getting the video capture resolution on screen "( When i connected pc hdmi output). I need to know the steps to see the screen of source in display window I will write the flow used to display from source ->There are three video frames namely 0,1,2 ->First I choose 6 ( index 0) then 5 ( Repeated for index 1 and 2) ->Later I choose 6 and then 8 ( i am getting blank image for all index) Note: Test pattern are successfully getting displayed ( for 3 and 4 option for all frame buffers)
  4. Hi sorry for long delay, I performed experiment for with and without EDID. while spying the signals by chip-scope for (data[23:0], hsync, vsync, data valid,pixel clock )signals at TX and Rx side. Following observations are 1. Output of RX side dvi2rgb IP core signals are not matching with the timing reference observed at TX side rbg2 DVI IP input( rgb input driven by Zynq pattern generator). 2. Pixel clock generated by dvi2rgb ip is 148.5 MHz and dynamic clock generator is 148.571 MHz 3. I connected the pc HDMI output as a input to HDMI RX . Still in the window hdmi unplugged is displayed kin teraterm window PFA given below the output of Debug ILA for the above two case. Debug_ila_output_screenshoots.docx
  5. I am happy that you understand my issue correctly.In the mentioned below I answered your questions 1.What Vivado version are you using? Ans : Version 2018.2. 2.Are you building the project yourself, or using the https://github.com/Digilent/Zybo-Z7-20-HDMI/releases? Ans : Yes, I am using the example program, you mentioned in the URL . 3.What is your test setup? Are you using HDMI or DVI sources? What resolutions are they using? What sinks (monitor) are you using? Ans : -> The video source is PHABRIX SX. -> The output of the source is SDI which is converted to HDMI using AJA converter ( Differential clock and data signals). -> I tried with formats 1080p60 (3G) and 720p60 (HD) NOTE: I changed the preferred resolution in IP 's accordingly(using UART prompt -teraterm) -> Monitor: DELL (3G compatible). 4.Does the monitor ever detect sync and lock to a resolution (even if the image is blank)? Ans: No. 5.How are you verifying the output of dvi2rgb? ILA? Do you have aPixelClkLckd=1, vde, hsync and vsync pulsing correctly? Ans: Yes, I verified using ILA by connecting dvi2rgb and rgb2dvi back to back without Znyq processor . The signals aPixelClkLckd=1, vde, hsync and vsync are pulsing correctly. But, Data is not in correct format ( If I apply red data i am not receiving ff0000), NOTE: 1.HDMI_RX_HPD is high when I connected the sink(Monitor) to HDMI_TX port by connecting dvi2rgb and rgb2dvi back to back. 2. when I am using the example program, once i choose option 5 (Start/Stop Video stream into Video Framebuffer) and i choose option 7(Grab Video Frame and invert colors) option 8(Grab Video Frame and scale to Display resolution). i am getting blank display and monitor is not detecting sync and lock to a resolution.
  6. Hi @JColvin, For Previous query( about ip dvi2rgb and rgb2dvi connected back to back). pls reply As Soon As Possible. Thanks, Guru
  7. Hi @JColvin, I connected dvi2rgb and rgb2dvi IP back to back without any application support and processor to check the working of those IP's. I observed that dvi2rgb seems to get junk data at the output of above mentioned when red data was given as input ( output RGB =FF0000 is expected), I also tested for other data like green and blue . I request you to check the same and reply ASAP.
  8. The code line 284 and 389 conveys about pixel clock and not associated with video capture
  9. Hi @JColvin, The teraterm window (uart prints) is displaying a HDMI UNPLUGGED in video capture resolution when i connect the video source i need to know why is it so??
  10. Hi @JColvin, In the above mentioned i am not getting the screenshot image even i choose option 5
  11. Hi @JColvin, Once I chose option 5 i.e start and stop video to buffer. I need to know which option to choose for displaying the frame to desktop. Regards, Guru Prasanth S
  12. Hi @JColvin, I need to know location of data coming from hdmi rx port that is stored in zynq processor through vdma ip form xilinx
  13. Hi, IN the link given (https://github.com/Digilent/Zybo-Z7-20-hdmi?_ga=2.136476851.289549728.1571318283-45849474.1563874383), where it demonstrates the functionality of hdmi TX and RX module. Option 5 (start/stop video streaming to video buffer). is not working and the input video is detected by hpd signal. Hence the clarity of functionality is needed. Need the complete functional description of the experiment.