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About jpotter0

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  1. My goal is to replace an embedded processor and interface logic for controlling an AD9959 DDS chip. I would like to enter data through a TCP/IP Ethernet link. There is a control computer that communicates with the controller with a LabVIEW interface. The function of the PS would be to load and read memory registers, possibly with some calculations in C. The PL would generate the control signals for the DDS. In addition the PL will implement an 8 channel pulse generator with individually programmable time delays and pulse widths. I think I know how to do the pulse generator if I can get the data into registers from Ethernet data. Any pointers to examples or suggestions about how to proceed would be greatly appreciated. Thanks, Jim
  2. Success! The LED is blinking. Now I can get on to learning how to do something with it. My initial goal is to make an 8 bit time base with the master clock rate adjustable 1 pps to 1000 pps by Ethernet command, and with each bit having an Ethernet programmable delay and pulse width with a resolution of 0.1 ns or better. If there is already a canned package that can do something like this or be modified to do it, I'd greatly appreciate any pointers. It's now past 3 AM, about the end of my evening. I will pursue this further in the morning. It turns out to have been a good choice to start with the Cora Z7. I tried the Trenz TE0723 and theTE0720 with the TE0705 test board. I could not make it through the tutorial without some kind of problem. It the tutorials are confusing or I'm easily confused. The Digilent tutorial is clear at every step. My only problem was being directed to Vivado 18.2 when 18.3 appears to work fine. - Jim
  3. Using Vivado 18.3 I got past that point. Someone needs to update the instructions. Now I will continue with the tutorial. So far the tutorial is more clear than the Trenz equivalent for their boards. - Jim
  4. I just got a Cora Z7-10 board. I'm tryin to follow the tutorial "Getting Started with Vivado." According to the information I saw I am supposed to be using Vivado 18.2. I have it installed as well as 18.3 and 19.1. I start out following the instructions, which seem very clear. Everything goes as expected through adding the constraints. The next step is to create a Verilog source file. I follow the directions through finish. Then the define Module window appears. I set clk as an input and led as an output, after previously editing the constraints file. After I click on OK and in a second or so the window disappears and Vivado shuts down. This has repeated 3 times, each time I am carefully following the instructions in the tutorial. What gives? Thanks - Jim