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  1. Thank you Zygot for the suggestions! I have tried pmod with jumper wires, it is easier to use than I expected. I just need to uncomment the ports from .xdc then use it just like regular input/output. And each of the 8 pins of one pmod connector can be use individually. Evo
  2. Thanks for the suggestion! I thought PMOD is only used for peripherals like sensors, LED, etc, didn't know we can use them to connect boards. So I only need a PMOD cable to connect 2 FPGA boards like this, correct? FPGA board 1 -- PMOD cable -- FPGA board2 I have Zybo, Basys 3 and Nexys 4, all 3 boards have PMOD interface. And is there any IPs needed inside FPGA to be used as RX/TX to drive the PMOD? Thanks, Evo
  3. I am working on a project that requires 2 FPGAs, one to be used as source, the other as sink, there are some low speed signals (less than 1Mhz) to be transferred between 2 boards. Is there any way to connect 2 FPGA boards? Which board/peripheral is needed? Thanks, Evo
  4. Thank you Andrew for the clear explanation! I finally debugged it out last night. The reset signal for some blocks in PL was massed up. Now the system works fine. Thanks, Hao
  5. Hi all, I asked a question about how to use DDR on Zybo previously here: https://forum.digilentinc.com/topic/1017-how-to-use-the-ddr-on-zybo/ Now, I can successfully use AXI_DMA to write and read video data into and out from on-board DDR. But still I have doubt about the DDR3-533 bandwidth in the reference manual: http://www.xilinx.com/support/documentation/university/XUP Boards/XUPZYBO/documentation/ZYBO_RM_B_V6.pdf On page-12, it says the bandwidth = 1066Mbps. So that's around 125MB/s. But I can successfully read one frame and write one frame of 720p video data at the same ti
  6. Those materials are great! Thank you Korken! Hao
  7. Thank you JColvin, Marshall and Hamster! Your replys are very helpful. I think my first step should be learning AXI and trying to configure PS. Then I will study what signal I should put on the AXI interface to read/write the DDR. Evocati
  8. Hi all, I am pretty new to FPGA design and wanna follow this tutorial(http://ece.wpi.edu/~rjduck/Microblaze MCS Tutorial v5.pdf) to create a "hello world" program through UART on Zybo. Basically, I wanna instantiate a microblaze MCS processor in PL and output its RX and TX signals to my laptop through UART. However, comparing Zybo with other board like Nexys4, there is no UART connection in XDC. (In XDC of Nexys4, there is TX/RX of UART connections.) For Zybo, TX/RX signals of UART is tied to PS MIO pins(read from chapter 6 of the Zybo manual). I tried to instantiate the
  9. Some updates about my question: Below are 3 IPs I found related: a) AXI Direct Memory Access b) AXI Video Direct Memory Access (Figure-3 on Zybo Manual points out that the DDR Controller is connected with Programmable Logic through "High Performance AXI ports") c) Memory Interface Generator (found in Vivado IP Catalog) I am so confused about the above 3 IPs. Which one should I use to access DDR? Thank you! Evocati
  10. Hi all, I am currently working on a video processing project and need to store frames of RGB signals into the DDR on the Zybo board. But it seems there is not many documents discussing how to use it. Here are the material I have read: 1) Zybo reference manual (doesn't cover much but mentions to read Zynq-7000 manual) 2) Chapter-10 of Zynq-7000 manual DDR memory controller ( focus a lot on the architecture, but not on how to use it) 3) The Zynq Book Tutorial (mentions DDR while introducing processing system) Can someone give me more directions on how to use t
  11. Evocati

    Zybo HDMI sink

    The problem is found and solved. The resolution in the default EDID(dgl_dvi_edid.txt) only support 3 resolutions: (https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_5/src) 1280x10241024x820800x640 However, none of them matches the resolutions my GoPro Hero3 supports.(https://gopro.com/support/articles/hero3-faqs) The demo project provided by digilent here(http://www.instructables.com/id/Quick-Start-Test-Demo-Zybo-Xlinx-Zynq-7000-Image-F/) has resolution 1280x720 and this is supported by GoPro. Whoever have similar problem should either modify the file dgl_dvi_edid.txt
  12. Evocati

    Zybo HDMI sink

    Thank you JColvin! Look forward to some good news. I will try to debug in the meantime. -Hao
  13. Hi Sam, Sorry to bother here since I have post so many questions recently on this forum. But I do find that what you mentioned here is the most urgent thing for newbies like me who has very limited experience on FPGA design. I found tons of documentations and answers for knowledge related to the GoPro project. Currently I'm trying to pass the signal through HDMI -> FPGA -> VGA. And the docs here in https://github.com/DigilentInc/vivado-library and discussions here https://forum.digilentinc.com/topic/560-help-with-a-zybo-video-design/#comment-1832 are extremely useful.
  14. Evocati

    Zybo HDMI sink

    Hi guys, Here are some more details about my situation. My current status is: 1) (success) Making the demo go pro project working, no coding needed. (http://www.instructables.com/id/Quick-Start-Test-Demo-Zybo-Xlinx-Zynq-7000-Image-F ) 2) (no success)Trying to reproduce Marshall's design I found in this post(https://forum.digilentinc.com/topic/560-help-with-a-zybo-video-design/#comment-1832). It's the first reply on that link. For short, the design tried to do this: Camera -> HDMI -> Zybo -> VGA -> monitor HDMI
  15. Evocati

    Zybo HDMI sink

    Hi guys, I just tried this project on my board and it works. And video information read from monitor is: resolution 1280x720 pixel clock 74.1MHz Since I am using the dvi2rgb core here. And in the documentation, page 7 "Default EDID", the above resolution is not supported by the default one. Does it mean that I need to modify the EDID part to add the above resolution in it so that my go pro can find the right data format? Thank you very much!! Hao