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  1. I have a PC which sends a 5 bytes of data to a PIC microcontroller. Byte 0 is the % character (lets pic know there is incoming data), byte 1 is ASCII "!" ( to identify that next incoming byte is to control the state of a single power relay), byte 2 ( is the power relay control data), byte 3 is ASCII "?" (used to signal that the next byte of data that will control one of several other mux relays), byte 4 is the mux relay data. Currently the Pic sends only byte 4 to the FPGA UART to control 1 of 43 mux relays. I would like to eliminate the Pic microcontroller all together and just use the FPGA (CMOD S6) to parse those 5 bytes and control all the relays. I'm not sure how to parse these 5 bytes by looking for ASCII characters %, !, and ?. Do I use case statement maybe? Any example on how something like this is done? Yes, I am new at FPGA's but not programming. It is probably simple but I'm drawing a blank on this because of lack of experience. Thanks for any suggestions, it is appreciated. I am doing this in VHDL.
  2. Thanks, Ana-Maria, the UART_RX_CTRL.vhd helped as I have it functioning now as needed. I didn't need to implement the 50Mhz clock but will try an add that later possibly. FPGA's are quite different then what I'm use to working with. Still don't have a full understanding of VHDL either, but I think I did pretty good for only working a week on it. You help was greatly appreciated, as well as the others who replied.
  3. Thank you for your help. I guess when I mentioned "clk16x" it is just arbitrary identifier for a clock input. Could have maybe just use "Clk" instead. This was not my code or work. That person who wrote it is no longer working at this company. Seeing I'm now the hardware and software programmer for them I have to get this code to work on a different FPGA now. I uploaded my project files if you interested in looking at them. I'll get this figured out eventually I think , or hope...
  4. The company I work for has several old Digilent Spartan 3 development boards that are still being used in some custom test equipment. I am tasked with finding a suitable replacement development board to create more of the same test equipment. The old Spartan 3 boards are no longer available. I chose the CMOD S6 which meets the requirements as a replacement. I have to tried to port over the old code to the new CMOD S6 board. The operation of the FPGA is to receive serial data from a Pic Microcontroller which is receiving RS232 data from software running on a computer. The computer basically sends ASCII data to the PIC that then in turn sends serial data to the FPGA telling it to turn on one of 42 relays in the equipment. I have plenty of programming experience in Pic Microcontrollers, Arduinos, and ARM processors, as well as computer software such as LabVIEW and more. I have very little experience in VHDL and FPGAs. The issue I am having is I ported over the code to the CMOD S6, programming both the FPGA and Flash device in Xilinx ISE and Impact. The UART receive is not working on the FPGA. I modified the constraints to work with the CMOD S6 assigning ports to their proper pins. I don't think I have the timing correct (clock) that is used for the Baud generator mainly because I just don't have a good understanding of the clock the FPGA uses. I don't have the code with me right now as I'm at home. The question I have is the code uses clk16x as the source of the timing for the baud generator. The clock on the CMOD S6 is 8mhz. Does that mean clk16x ( which is clk16x : IN std_logic) is also at 8Mhz? Do I need to somehow define how clk16x gets it's timing or clock from? Maybe in timing constraints? Originally the clock on the old Spartan board was 50Mhz and the Baud generator used that for calculating the baud rate. Now I working with an system clock of 8Mhz. There is a way to create a 50mhz clock for the baud generator but I'm not sure how to do that yet and have it go to clk16x input. Help would be greatly appreciated. I'll attach the code later if needed.