trian

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Everything posted by trian

  1. trian

    image processing in vhdl

    Thank you for your answer, I think I corrected that part but now, I cannot get anything out from the block ram. I wrote the code for comparing datas from the other 2 roms and then write the desired data to a block ram. I simulated it, In simulation, the bits are correct and I can read them but when I connect the vga, then I only get black screen (i check the sync signals, i can get green screen and such). So i thought maybe the timing is wrong, because at the time vga starts, the comparison between the roms are made and the data is not ready yet in the block ram. What can I do? How can I read the block ram (i think it has the correct pixels starting from the address 0016(in hex))? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity image_process is port( clk: in std_logic; LED1: out std_logic ); end image_process; architecture Behavioral of image_process is COMPONENT image1 PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT image2 PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT image3 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; signal done : std_logic := '0'; signal addr_rom1, addr_rom2, addr_ram : STD_LOGIC_VECTOR(14 DOWNTO 0) := (others => '0'); signal data_rom1, data_rom2, data_in_ram, data_out_ram: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); signal row_index,col_index : integer := 0; signal wr_enable : std_logic_vector(0 downto 0) := (others => '1'); begin image_rom1 : image1 port map(Clk,addr_rom1,data_rom1); image_rom2 : image2 port map(Clk,addr_rom2,data_rom2); image_ram : image3 port map(Clk,wr_enable,addr_ram,data_in_ram,data_out_ram); process(clk) begin if(falling_edge(clk)) then if(done = '0') then addr_rom1 <= addr_rom1 + "1"; --start reading each pixel from rom addr_rom2 <= addr_rom2 + "1"; --row and column index of the image. if(col_index = 15) then --check if last column has reached col_index <= 0; --reset it to zero. if(row_index = 1199) then --check if last row has reached. row_index <= 0; --reset it to zero done <= '1'; --the processing is done. else row_index <= row_index + 1; --increment row index. end if; else col_index <= col_index + 1; --increment column index. end if; wr_enable <= "1"; --write enable for the RAM if (data_rom1 = X"5C") then data_in_ram <= data_rom2; --store the current read data from rom into ram. else data_in_ram <= data_rom1; end if; addr_ram <= addr_rom1; --set the address for RAM. end if; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top_module is Port ( clk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(1 downto 0); vgaBlue : out STD_LOGIC_VECTOR(3 downto 0); vgaGreen : out STD_LOGIC_VECTOR(3 downto 0); vgaRed : out STD_LOGIC_VECTOR(3 downto 0); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC ); end top_module; architecture Behavioral of top_module is component synchronization is Port( clk : in STD_LOGIC; vectorBlue : in STD_LOGIC_VECTOR(3 downto 0); vectorGreen : in STD_LOGIC_VECTOR(3 downto 0); vectorRed : in STD_LOGIC_VECTOR(3 downto 0); vgaBlue : out STD_LOGIC_VECTOR(3 downto 0); vgaGreen : out STD_LOGIC_VECTOR(3 downto 0); vgaRed : out STD_LOGIC_VECTOR(3 downto 0); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC ); end component; COMPONENT image3 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; component clk_wiz_0 is Port ( clk50 : out STD_LOGIC; clk100 : out STD_LOGIC; clk : in STD_LOGIC ); end component; signal vectorBlue : STD_LOGIC_VECTOR(3 downto 0); signal vectorGreen : STD_LOGIC_VECTOR(3 downto 0); signal vectorRed : STD_LOGIC_VECTOR(3 downto 0); signal addra : STD_LOGIC_VECTOR(14 DOWNTO 0):=(others=>'0'); signal dina : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others=>'0'); signal douta : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others=>'0'); signal wr_enable : std_logic_vector(0 downto 0) := (others => '1'); signal clk50: std_logic; signal clk100: std_logic; begin clock: clk_wiz_0 port map(clk50, clk100, clk); image_ram : image3 port map(Clk50,wr_enable,addra,dina,douta); process(sw,douta,clk100) is begin if sw(1) = '1' then wr_enable <= "0"; --after processing write enable is disabled addra <= "000000000010110"; if (rising_edge (clk100)) then if(addra = "100101011111111") then addra <= "000000000000000"; else addra <= addra + 1; end if; vectorBlue(3) <= douta(0); vectorBlue(2) <= douta(1); vectorBlue(1) <= '0'; vectorBlue(0) <= '0'; vectorGreen(3) <= douta(2); vectorGreen(2) <= douta(3); vectorGreen(1) <= douta(4); vectorGreen(0) <= '0'; vectorRed(3) <= douta(5); vectorRed(2) <= douta(6); vectorRed(1) <= douta(7); vectorRed(0) <= '0'; end if; elsif sw(0) ='1' then vectorBlue <= "0000"; vectorGreen <="1111"; vectorRed <= "0000"; end if; end process; sync: synchronization port map (clk => clk100, vectorBlue => vectorBlue, vectorGreen => vectorGreen, vectorRed => vectorRed, vgaBlue => vgaBlue, vgaGreen => vgaGreen, vgaRed => vgaRed, Hsync => Hsync, Vsync => Vsync ); end Behavioral;
  2. trian

    image processing in vhdl

    Hello, I'm trying to do image processing on BASYS3 using VHDL. I have 2 pictures, 1 with the green background and the other as the background image to change the greens in the first picture. I uploaded those 2 pictures into 2 single port rom using coe files and now trying to compare the bits in the addresses to write the chosen data in a RAM. The code I have: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity image_process is end image_process; architecture Behavioral of image_process is COMPONENT image1 PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT image2 PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT image3 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; signal done,clk : std_logic := '0'; signal wr_enable : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0"; signal addr_rom1, addr_rom2, addr_ram : STD_LOGIC_VECTOR(14 DOWNTO 0) := (others => '0'); signal data_rom1, data_rom2, data_in_ram, data_out_ram : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others => '0'); signal row_index,col_index : integer := 0; begin image_rom1 : image1 port map(Clk,addr_rom1,data_rom1); image_rom2 : image2 port map(Clk,addr_rom2,data_rom2); image_ram : image3 port map(Clk,wr_enable,addr_ram,data_in_ram,data_out_ram); clk <= not clk after 5 ns; process(clk) begin if(falling_edge(clk)) then if(done = '0') then addr_rom1 <= addr_rom1 + "1"; --start reading each pixel from rom addr_rom2 <= addr_rom2 + "1"; if(col_index = 15) then --check if last column has reached col_index <= 0; --reset it to zero. if(row_index = 19199) then --check if last row has reached. row_index <= 0; --reset it to zero done <= '1'; --the processing is done. else row_index <= row_index + 1; --increment row index. end if; else col_index <= col_index + 1; --increment column index. end if; wr_enable <= "1"; --write enable for the RAM if (data_rom1 <= (x"1C" or x"14" or x"5C")) then data_in_ram <= data_rom2; else data_in_ram <= data_rom1; end if; addr_ram <= addr_rom1; --set the address for RAM. else wr_enable <= "0"; --after processing write enable is disabled addr_rom1 <= "000000000000000"; if(addr_ram = "100101011111111") then addr_ram <= "000000000000000"; else addr_ram <= addr_ram + 1; end if; end if; end if; end process; end Behavioral; one of the coe files is attached. I'm getting the error as "The design is empty." and I don't know how to fix it. Can someone help? catgreen.coe.coe
  3. trian

    OV7670 and BASYS3

    Hello, I am trying to do chroma-keying using BASYS3. I want to take data from OV7670 and replace the green pixels with the pixels of an image previously loaded to block ram. However, I did not understand how can I capture only one frame like taking a picture with OV7670. I used the code here: https://www.fpga4student.com/2018/08/basys-3-fpga-ov7670-camera.html (I am a newbie at FPGA)
  4. trian

    Basys3 Memory

    Thank you so much for your answers. Now at least I know what to look for. I am trying to do the green screen effect using BASYS3. I thought I can get the background image that will replace the green screen from a computer by the connection from UART but at first, I think I need to convert the image into a binary text file for BASYS3. Then, by the help of a camera (OV7670), I think I can get the foreground object's data. OV7670 already gives me 640x480 pixel image at most. So, by compressing the image (like 1 pixel for every 4 pixel), blockRAM should be enough I guess?
  5. trian

    Basys3 Memory

    For a project, I need to store the data comes from a camera and another data image from a laptop in Basys3. I am quite new at these stuff so I couldn't be sure if I can store both of them to make effects and combine them. Can I do it on Basys3? Can SPI Flash memory and SRAM based memory cells in it be used?