weilai

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  1. Thanks for your explaination. but I'm a Beginer of RAM, so it's difficult for me to understand you. forget all of them, now I just want to get access to the SDRAM on my ARTY--7-35 board. I mean, send data to external SDRAM on my board from PC and receive them, through UART communication. Now I have successfully built my "send and receive"uart module, what should I do next? Thanks, Dehao
  2. >>1: it's arty A7-35t Board >>2: I'm trying to connect with the DDR3 SDRAM chip on the board. I try to avoid IP core and I want to build my module directly, but it seems almost all the tutorials are about how to access the memory by IP core. >>3: no, I haven't simulated my design. But the problem now is I can not access the coorect pin number of the DDR3 from the ARTY achematic. the pin number of DDR seems interface with other pin muber. but thanks for your tutorial. >>4: I really want to know what's the problem with my contraints for DDR3. And I will upload image instead of ppt. Thanks a lot
  3. Hi, guys: I'm currently doing the '' write and read RAM'' project, in which I want to send characters to RAM through UART, and then read the data from the ram. I find two problems: 1.pin assignment of RAM. is there the pin number of ram in ARTY achematic, but it seems the pin number interfaced with other pin or isn't vaild.I show this problem in my slide in the attachment. for example, pin'C2' for reset also occurs in a pin of DDR3 in the achematic file. 2. the voltage required for RAM is around 1.5V, but it's 3.3V for other parts like clk or button. so when I set up my contraints, and some error occurs. I put the error module uart_top( input sys_clk, //system clk 100MHz input sys_rst_n, //reset //uart接口 input uart_rxd, //UART receive port output uart_txd, //UART send port input we, input re, input [2:0] addr, input [7:0]wr_data ); //parameter define parameter CLK_FREQ = 100000000; //sys_clk parameter UART_BPS = 115200; //bps //wire define wire uart_en_w; //UART_send_enable wire [7:0] uart_data_w; //UART send data wire clk_1m_w; wire [7:0] mem_data; //***************************************************** //** main code //***************************************************** //串口接收模块 例化 uart_recv #( //parameter revalue .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口接收波特率 ) u_uart_recv( //串口接收模块 .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .uart_rxd (uart_rxd), .uart_done (uart_en_w), .uart_data (uart_data_w) ); //串口发送模块 例化 uart_send #( //parameter重新赋值 .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口发送波特率 ) u_uart_send( //串口发送模块 .sys_clk (sys_clk), .sys_rst_n (sys_rst_n), .uart_en (uart_en_w), .uart_din (mem_data), .uart_txd (uart_txd) ); uart_ram #( //parameter重新赋值 .CLK_FREQ (CLK_FREQ), //设置系统时钟频率 .UART_BPS (UART_BPS) //设置串口接收波特率 ) u_uart_ram( //ram connect to uart .clk (sys_clk), .we (we), .re (re), .addr (addr), .wr_data (uart_data_w), .dout (mem_data) ); endmodule module uart_recv( input sys_clk, input sys_rst_n, input uart_rxd, output reg uart_done, //接收一帧数据完成标志信号 output reg [7:0] uart_data //接收的数据 ); //parameter define parameter CLK_FREQ = 100000000; //系统时钟频率 50M parameter UART_BPS = 115200; //串口波特率 localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率, //需要对系统时钟计数BPS_CNT次 //reg define reg uart_rxd_d0; reg uart_rxd_d1; reg [15:0] clk_cnt; reg [ 3:0] rx_cnt; reg rx_flag; reg [ 7:0] rxdata; //wire define wire start_flag; //***************************************************** //** main code //***************************************************** //************************************************************************************************* assign start_flag = uart_rxd_d1 & (~uart_rxd_d0); always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_rxd_d0 <= 1'b0; uart_rxd_d1 <= 1'b0; end else begin uart_rxd_d0 <= uart_rxd; uart_rxd_d1 <= uart_rxd_d0; end end //************************************************************************************************ //***************************************************************************************************** always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) rx_flag <= 1'b0; else begin if(start_flag) rx_flag <= 1'b1; else if((rx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) rx_flag <= 1'b0; else rx_flag <= rx_flag; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin clk_cnt <= 16'd0; rx_cnt <= 4'd0; end else if ( rx_flag ) begin if (clk_cnt < BPS_CNT - 1) begin clk_cnt <= clk_cnt + 1'b1; rx_cnt <= rx_cnt; end else begin clk_cnt <= 16'd0; rx_cnt <= rx_cnt + 1'b1; end end else begin clk_cnt <= 16'd0; rx_cnt <= 4'd0; end end //***************************************************************************************************** always @(posedge sys_clk or negedge sys_rst_n) begin if ( !sys_rst_n) rxdata <= 8'd0; else if(rx_flag) if (clk_cnt == BPS_CNT/2) begin case ( rx_cnt ) 4'd1 : rxdata[0] <= uart_rxd_d1; 4'd2 : rxdata[1] <= uart_rxd_d1; 4'd3 : rxdata[2] <= uart_rxd_d1; 4'd4 : rxdata[3] <= uart_rxd_d1; 4'd5 : rxdata[4] <= uart_rxd_d1; 4'd6 : rxdata[5] <= uart_rxd_d1; 4'd7 : rxdata[6] <= uart_rxd_d1; 4'd8 : rxdata[7] <= uart_rxd_d1; default:; endcase end else rxdata <= rxdata; else rxdata <= 8'd0; end // always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_data <= 8'd0; uart_done <= 1'b0; end else if(rx_cnt == 4'd9) begin uart_data <= rxdata; uart_done <= 1'b1; //并将接收完成标志位拉高 end else begin uart_data <= 8'd0; uart_done <= 1'b0; end end endmodule module uart_ram(//clk,we,re,addr,dout,wr_data input clk, input we, input re, input [2:0] addr, output reg [7:0] dout, input [7:0]wr_data ); parameter ADD_WIDTH=3; parameter DATA_WIDTH=8; /*input clk; input we; input re; input [2:0] addr; output reg [7:0] dout; input [7:0]wr_data;*/ //output reg [7:0] mod; parameter CLK_FREQ = 100000000; //system clock parameter UART_BPS = 115200; //port bps localparam BPS_CNT = CLK_FREQ/UART_BPS; //BPS_CNT reg[DATA_WIDTH-1:0] mem [2**ADD_WIDTH-1:0]; always@(posedge clk) begin if (we) begin mem[addr]<=wr_data; end end always@(posedge clk) begin if (re && !we) begin dout= mem[addr]; // mod= dout[7:0]; end else begin dout=8'd0; //mod=8'd0; end end endmodule module uart_send( input sys_clk, //系统时钟 input sys_rst_n, //系统复位,低电平有效 input uart_en, //发送使能信号 input [7:0] uart_din, //待发送数据 output reg uart_txd //UART发送端口 ); //parameter define parameter CLK_FREQ = 100000000; //系统时钟频率 parameter UART_BPS = 115200; //串口波特率 localparam BPS_CNT = CLK_FREQ/UART_BPS; //为得到指定波特率,对系统时钟计数BPS_CNT次 //reg define reg uart_en_d0; reg uart_en_d1; reg [15:0] clk_cnt; reg [ 3:0] tx_cnt; reg tx_flag; reg [ 7:0] tx_data; //wire define wire en_flag; //***************************************************** //** main code assign en_flag = (~uart_en_d1) & uart_en_d0; always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin uart_en_d0 <= 1'b0; uart_en_d1 <= 1'b0; end else begin uart_en_d0 <= uart_en; uart_en_d1 <= uart_en_d0; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin tx_flag <= 1'b0; tx_data <= 8'd0; end else if (en_flag) begin tx_flag <= 1'b1; tx_data <= uart_din; end else if ((tx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) begin tx_flag <= 1'b0; tx_data <= 8'd0; end else begin tx_flag <= tx_flag; tx_data <= tx_data; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin clk_cnt <= 16'd0; tx_cnt <= 4'd0; end else if (tx_flag) begin if (clk_cnt < BPS_CNT - 1) begin clk_cnt <= clk_cnt + 1'b1; tx_cnt <= tx_cnt; end else begin clk_cnt <= 16'd0; tx_cnt <= tx_cnt + 1'b1; end end else begin //发送过程结束 clk_cnt <= 16'd0; tx_cnt <= 4'd0; end end always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) uart_txd <= 1'b1; else if (tx_flag) case(tx_cnt) 4'd0: uart_txd <= 1'b0; 4'd1: uart_txd <= tx_data[0]; 4'd2: uart_txd <= tx_data[1]; 4'd3: uart_txd <= tx_data[2]; 4'd4: uart_txd <= tx_data[3]; 4'd5: uart_txd <= tx_data[4]; 4'd6: uart_txd <= tx_data[5]; 4'd7: uart_txd <= tx_data[6]; 4'd8: uart_txd <= tx_data[7]; 4'd9: uart_txd <= 1'b1; default: ; endcase else uart_txd <= 1'b1; end endmodule massage in the attachment too. 1.pptx error massage.txt
  4. Hi guys, happy new year!! I'm currently trying to write and read data from my DDR3 SDRAM block. Instead of using any IP core, I want to write and read data diractly using Verilog in Vivado. But unforunitely, I can't find the XDC configition in XDC file of my board. so I'm stucking at how t `timescale 1ns / 1ps //ram.v module ram( input clk_i, input rst_i, input wr_en_i, input rd_en_i, input [7:0] addr_i, inout [31:0] data_io ); reg [31:0] bram[255:0]; integer i; reg [31:0] data; //add implementation code here always @(posedge clk_i or posedge rst_i) begin if (rst_i) begin for(i=0;i<=255;i=i+1) //reset bram[i] <= 32'b0; end else if (wr_en_i) begin bram[addr_i] <= data_io; end else if (rd_en_i) begin data <= bram[addr_i]; end else begin data <= 32'bz; end end assign data_io = rd_en_i? data : 32'bz; endmodule Mater xdc file for arty-35.txto realize my XDC. The attachment is DDR3 CIRCUIT, XDC file and My verilog code
  5. yes, actuaclly I'm trying to use python code to send some characters to board and make the led blinking. can you offer me links of tutorials about this.
  6. thanks for your kind reply! I have a uart receiver application which can receive chracters from PC and then make specific led blinking in FPGA. This function can be realized when I send characters through TeraTerm. However, When I try to send by Python code as follows it don't work.So how should I do if I want send characters with python to board and blink led like using TeraTerm. Python code: import serial ser = serial.Serial("com9",9600,timeout=0.01) c=input("o") ser.write(c.encode()) ser.close() uart receiver code: `timescale 1ns / 1ps module receiver( input clk, //input clock input reset, //input reset input RxD, //input receving data line output [7:0]RxData, // output for 8 bits data output LED01, // output 8 LEDs output LED02 ); //internal variables reg shift; // shift signal to trigger shifting data reg state, nextstate; // initial state and next state variable reg [3:0] bitcounter; // 4 bits counter to count up to 9 for UART receiving reg [1:0] samplecounter; // 2 bits sample counter to count up to 4 for oversampling reg [13:0] counter; // 14 bits counter to count the baud rate reg [9:0] rxshiftreg; //bit shifting register reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //clear or increment the counter assign LED01=shift; assign LED02=nextstate; // constants parameter clk_freq = 100_000_000; // system clock frequency parameter baud_rate = 9_600; //baud rate parameter div_sample = 4; //oversampling parameter div_counter = clk_freq/(baud_rate*div_sample); // this is the number we have to divide the system clock frequency to get a frequency (div_sample) time higher than (baud_rate) parameter mid_sample = (div_sample/2); // this is the middle point of a bit where you want to sample it parameter div_bit = 10; // 1 start, 8 data, 1 stop assign RxData = rxshiftreg [8:1]; // assign the RxData from the shiftregister //UART receiver logic always @ (posedge clk) begin if (!reset)begin // if reset is asserted state <=1; // set state to idle bitcounter <=0; // reset the bit counter counter <=0; // reset the counter samplecounter <=0; // reset the sample counter end else begin // if reset is not asserted counter <= counter +1; // start count in the counter if (counter >= div_counter-1) begin // if counter reach the baud rate with sampling counter <=0; //reset the counter state <= nextstate; // assign the state to nextstate if (shift)rxshiftreg <= {RxD,rxshiftreg[9:1]}; //if shift asserted, load the receiving data if (clear_samplecounter) samplecounter <=0; // if clear sampl counter asserted, reset sample counter if (inc_samplecounter) samplecounter <= samplecounter +1; //if increment counter asserted, start sample count if (clear_bitcounter) bitcounter <=0; // if clear bit counter asserted, reset bit counter if (inc_bitcounter)bitcounter <= bitcounter +1; // if increment bit counter asserted, start count bit counter end end end //state machine always @ (posedge clk) //trigger by clock begin shift <= 0; // set shift to 0 to avoid any shifting clear_samplecounter <=0; // set clear sample counter to 0 to avoid reset inc_samplecounter <=0; // set increment sample counter to 0 to avoid any increment clear_bitcounter <=0; // set clear bit counter to 0 to avoid claring inc_bitcounter <=0; // set increment bit counter to avoid any count nextstate <=1; // set next state to be idle state case (state) 0: begin // idle state if (RxD) // if input RxD data line asserted begin nextstate <=0; // back to idle state because RxD needs to be low to start transmission end else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end 1: begin // receiving state nextstate <= 1; // DEFAULT if (samplecounter== mid_sample-1) shift <= 1; // if sample counter is 1, trigger shift //LED<=1; if (samplecounter== div_sample - 1) begin // if sample counter is 3 as the sample rate used is 3 if (bitcounter == div_bit - 1) begin // check if bit counter if 9 or not nextstate <= 0; // back to idle state if bit counter is 9 as receving is complete end inc_bitcounter <=1; // trigger the increment bit counter if bit counter is not 9 clear_samplecounter <=1; //trigger the sample counter to reset the sample counter end else inc_samplecounter <=1; // if sample is not equal to 3, keep counting end default: nextstate <=0; //default idle state endcase end endmodule Thanks, Dehao
  7. Hi,guys! I'm currently working on how to send character"hello" to FPGA and then transmit "hello" back to my PC. But it seems I only can send some characters to my board and cannot receive the chracters back to PC. I wonder how to build my code in python to get the characters back to my PC. The attachment is my code(PYTHON) and result of runing. import serial ser = serial.Serial("com9",9600,timeout=0.25) print(ser.name) print(ser.port) #ser.open() c=input("hello") b=ser.isOpen() s=ser.read(10) ser.write(c.encode()) print(s) print(b) ser.close() Thanks, Dehao
  8. thanks so much. this really help me out!!!
  9. Hi,guys, I'm new and I have some problems in uart communication with PC(windows). I built UART RX (receiving) hardware. 8 LEDs will be used to show the binary value of the ASCII character. When the key strobe on the keyboard (from the computer) is pressed, the 8 bits will transmit from the keyboard to FPGA through USB-UART port on arty-7-35T board. However, when I send something to board through TERATERM, all the LED is always off. when I connect one LED to RxD, the LED is always on. the following is my code. `timescale 1ns / 1ps module receiver( input clk, //input clock input reset, //input reset input RxD, //input receving data line output [7:0]RxData, // output for 8 bits data output LED01, // output 8 LEDs output LED02 ); //internal variables reg shift; // shift signal to trigger shifting data reg state, nextstate; // initial state and next state variable reg [3:0] bitcounter; // 4 bits counter to count up to 9 for UART receiving reg [1:0] samplecounter; // 2 bits sample counter to count up to 4 for oversampling reg [13:0] counter; // 14 bits counter to count the baud rate reg [9:0] rxshiftreg; //bit shifting register reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //clear or increment the counter assign LED01=shift; assign LED02=nextstate; // constants parameter clk_freq = 100_000_000; // system clock frequency parameter baud_rate = 9_600; //baud rate parameter div_sample = 4; //oversampling parameter div_counter = clk_freq/(baud_rate*div_sample); // this is the number we have to divide the system clock frequency to get a frequency (div_sample) time higher than (baud_rate) parameter mid_sample = (div_sample/2); // this is the middle point of a bit where you want to sample it parameter div_bit = 10; // 1 start, 8 data, 1 stop assign RxData = rxshiftreg [8:1]; // assign the RxData from the shiftregister //UART receiver logic always @ (posedge clk) begin if (reset)begin // if reset is asserted state <=1; // set state to idle bitcounter <=0; // reset the bit counter counter <=0; // reset the counter samplecounter <=0; // reset the sample counter end else begin // if reset is not asserted counter <= counter +1; // start count in the counter if (counter >= div_counter-1) begin // if counter reach the baud rate with sampling counter <=0; //reset the counter state <= nextstate; // assign the state to nextstate if (shift)rxshiftreg <= {RxD,rxshiftreg[9:1]}; //if shift asserted, load the receiving data if (clear_samplecounter) samplecounter <=0; // if clear sampl counter asserted, reset sample counter if (inc_samplecounter) samplecounter <= samplecounter +1; //if increment counter asserted, start sample count if (clear_bitcounter) bitcounter <=0; // if clear bit counter asserted, reset bit counter if (inc_bitcounter)bitcounter <= bitcounter +1; // if increment bit counter asserted, start count bit counter end end end //state machine always @ (posedge clk) //trigger by clock begin shift <= 0; // set shift to 0 to avoid any shifting clear_samplecounter <=0; // set clear sample counter to 0 to avoid reset inc_samplecounter <=0; // set increment sample counter to 0 to avoid any increment clear_bitcounter <=0; // set clear bit counter to 0 to avoid claring inc_bitcounter <=0; // set increment bit counter to avoid any count nextstate <=1; // set next state to be idle state case (state) 0: begin // idle state if (RxD) // if input RxD data line asserted begin nextstate <=0; // back to idle state because RxD needs to be low to start transmission end else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end 1: begin // receiving state nextstate <= 1; // DEFAULT if (samplecounter== mid_sample-1) shift <= 1; // if sample counter is 1, trigger shift //LED<=1; if (samplecounter== div_sample - 1) begin // if sample counter is 3 as the sample rate used is 3 if (bitcounter == div_bit - 1) begin // check if bit counter if 9 or not nextstate <= 0; // back to idle state if bit counter is 9 as receving is complete end inc_bitcounter <=1; // trigger the increment bit counter if bit counter is not 9 clear_samplecounter <=1; //trigger the sample counter to reset the sample counter end else inc_samplecounter <=1; // if sample is not equal to 3, keep counting end default: nextstate <=0; //default idle state endcase end endmodule