[Removing debug logic of pcam-5c reference design]

Thanks,

Can you please explain what you mean by

Quote

"checking out the sources"

?

[Removing debug logic of pcam-5c reference design]

Why doesn't this post get any attention ?

I pointed out and showed an example of a clear problem

[Removing debug logic of pcam-5c reference design]

 You can see the process here:

 

[Removing debug logic of pcam-5c reference design]

I'm not familiar with this script.

What I did - is simply download the 2018.2-2 project version from this page:

https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases

1. Can this cause my project to malfunction ?

2. What are the benefits of using this  Python script ?

[Removing debug logic of pcam-5c reference design]

I tried it with 2018.2 and got EXACTLY the same problem.

 

 

[Removing debug logic of pcam-5c reference design]

Thanks.

I'll try it with 2018.2

Meanwhile. I managed to workaround the problem by accessing manually changing the HDL inside file: system_MIPI_CSI_2_RX_0_0.vhd

Which is located in:

C:\Zybo-Z7-20-pcam-5c-2017.4-1\src\bd\system\ip\system_MIPI_CSI_2_RX_0_0\synth\system_MIPI_CSI_2_RX_0_0.vhd

 

 

 

[Removing debug logic of pcam-5c reference design]

Hi,

1. If you downloaded the 2017.4 project version from GIT - and tried to compile it in the same version - why did it ask for an IP upgrade ?

2. Did you try to un-check the "Debug Module" box for the MIPI CSI-2 and re-compile ? Did it work ?

 

[Removing debug logic of pcam-5c reference design]

Hello,

I'm trying to modify the pcam-5c design for the Zybo board (Vivado 2017.4).
The design takes up a lot of logic for debug especially in MIPI_CSI2_Rx.vhd.
I tried removing this logic by un-checking the "Debug Module" box of the "MIPI CSI-2 Receiver" core inside the supplied block design.

I saved the design and re-run synthesis - which failed with the following message :

Quote

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

Re-checking the "Debug Module" box are re-synthesizing didn't solve the problem.

The only thing that fixed the problem is copying the \src\bd\system\ip\system_MIPI_CSI_2_RX_0_0 folder from a mirror ( untouched ) design.

2 questions:

1. How did un-checking the "Debug Module" box cause the design to break in such irreversible way?
2. How can I reliably remove the ILA debug logic ?