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  1. Hello, While trying to compile (a modified version of) the 18.2 Zybo PCAM 5 demo inside the SDK I got the following error: no matches converting function 'MyCallback' to type 'XIicPs_IntrHandler {aka void (*)(void*, long unsigned int)}' The error pointed to the following line of code in a file named PS_IIC.h : XIicPs_SetStatusHandler (&drv_inst_, &stat_handler_, &MyCallback<void(int)>); Please explain this error. Notes: 1. The Vivado project compiled correctly and the hardware was exported successfully to the SDK. 2. The PS_IIC.h file and a snapshot of the error message are attached. PS_IIC.h
  2. I'm not familiar with this script. What I did - is simply download the 2018.2-2 project version from this page: 1. Can this cause my project to malfunction ? 2. What are the benefits of using this Python script ?
  3. I tried it with 2018.2 and got EXACTLY the same problem.
  4. Thanks. I'll try it with 2018.2 Meanwhile. I managed to workaround the problem by accessing manually changing the HDL inside file: system_MIPI_CSI_2_RX_0_0.vhd Which is located in: C:\Zybo-Z7-20-pcam-5c-2017.4-1\src\bd\system\ip\system_MIPI_CSI_2_RX_0_0\synth\system_MIPI_CSI_2_RX_0_0.vhd
  5. Hi, 1. If you downloaded the 2017.4 project version from GIT - and tried to compile it in the same version - why did it ask for an IP upgrade ? 2. Did you try to un-check the "Debug Module" box for the MIPI CSI-2 and re-compile ? Did it work ?
  6. Hello, I'm trying to modify the pcam-5c design for the Zybo board (Vivado 2017.4). The design takes up a lot of logic for debug especially in MIPI_CSI2_Rx.vhd. I tried removing this logic by un-checking the "Debug Module" box of the "MIPI CSI-2 Receiver" core inside the supplied block design. I saved the design and re-run synthesis - which failed with the following message : Re-checking the "Debug Module" box are re-synthesizing didn't solve the problem. The only thing that fixed the problem is copying the \src\bd\system\ip\system_MIPI_CSI_2_RX_0_0 folder from a mirror ( untouched ) design. 2 questions: 1. How did un-checking the "Debug Module" box cause the design to break in such irreversible way? 2. How can I reliably remove the ILA debug logic ?
  7. Thanks a lot for your kind help. Please stay posted - I'll update on my progress and will definitely have more questions as I progress.
  8. Well...the software application that controls the logic design might set any X * Y combination - Even "very strange" sizes such as for example: X= 1000, Y = 1. So I must be able to support all possible matrix sizes. According to what you say - the sensor DOES support I correct ? But I'm not sure the VDMA does. I might have to remove this IP from the design altogether and write something custom.
  9. I understand. Thanks. I'm using the reference design's infrastructure as a basis to achieve different operation. What I need to do is record (single) raw images to the Zynq's memory upon software request. The output to the monitor isn't necessary so the whole Tx path can be discarded. Now, in my case - the resolutions the Zynq might request can be quite arbitrary and not limited to a set of standard image sizes ( basically any X * Y within the sensor's limits ). A few questions: 1. Would the sensor support output of an arbitrary image size configured using its registers ? 2. What about the other IP's in the design ?
  10. Thanks a lot for your input Bogdan. Unfortunately, using the Scaller IP isn't an option - changing the actual resolution that the sensor outputs is a mandatory project requirement. Can you explain what you mean by "Video Trimming Controller IP" ? I can't find such a component in the Vivado PCAM 5C reference design...
  11. Hello, I'm trying to change the resolution of the Pcam 5C using the Zybo's reference design via a UART console. The console application supports 3 pre-configured resolution setting changeable by typing 'a' and then the setting number. But I want to change it manually via accessing the Pcam 5C's internal ISP registers - as described in page 41 in the datasheet: Question: Can the resolution be changed solely by changing the value of these registers "on the fly" ? Or is a complete initialization sequence required ?