bitslip

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  1. Thanks, Can you please explain what you mean by ?
  2. Why doesn't this post get any attention ? I pointed out and showed an example of a clear problem
  3. Hello, I'm working with the Zybo Pcam 5C (18.2) reference design. While using the default resolution of 1920 * 1080 - I observe the AXI Stream but exiting from the GAMA CORRECTION IP (this is last core in the video chain before the VDMA). A strange thing I noticed is that the first 4 lines at the beginning of each frame are a constant 0xAE for all pixels. ( all the red , green and blue pixels have the same value which is 0xAE ). After the first 1920 * 4 pixels non - constant data starts to arrive. Why is this ? Is this the way the sensor outputs data ?
  4. Thanks! This post of the same project also awaits your kind attention:
  5. I did something a little different. I looked at AXI_VDMA.h file and change the contents of PS_IIC.h to be more like it. This is what I did: // I changed the original function prototype : template <typename Func> void MyCallback(void* CallbackRef, int i) { auto pfn = static_cast<std::function<Func>*>(CallbackRef); pfn->operator()(i); } // To this : template <typename Func> void MyCallback(void* CallbackRef, uint32_t mask_or_type) { auto pfn = static_cast<std::function<Func>*>(CallbackRef); pfn->operator()(mask_or_type); } //////////////////////////////////////////////////////////////////////////////////////////////////// // And I changed the original function call : XIicPs_SetStatusHandler (&drv_inst_, &stat_handler_, &MyCallback<void(int)>); // To this : XIicPs_SetStatusHandler (&drv_inst_, &stat_handler_, &MyCallback<void(uint32_t)>); It now compiles well. Can you explain why it didn't work and this solved it ?
  6. This is a snapshot of the settings.
  7. It's a typo - the project IS defined as C++ I'd like to add that NO changes where made to the offending file named: PS_IIC.h It's EXACTLY the same as in the original project.
  8. Hi Ana-Maria, 10 days past since my last post - so I was beginning to loose hope... Thanks for stepping in. Yes I did. By "modified version" I mean that I changed the logic design in Vivado and re-exported the hardware to SDK. When I tried to re-compile the C code inside SDK - I got many errors in various C and Header files. I managed to fix all - except of the one in this post.
  9. Hello, While trying to compile (a modified version of) the 18.2 Zybo PCAM 5 demo inside the SDK I got the following error: no matches converting function 'MyCallback' to type 'XIicPs_IntrHandler {aka void (*)(void*, long unsigned int)}' The error pointed to the following line of code in a file named PS_IIC.h : XIicPs_SetStatusHandler (&drv_inst_, &stat_handler_, &MyCallback<void(int)>); Please explain this error. Notes: 1. The Vivado project compiled correctly and the hardware was exported successfully to the SDK. 2. The PS_IIC.h file and a snapshot of the error message are attached. PS_IIC.h
  10. I'm not familiar with this script. What I did - is simply download the 2018.2-2 project version from this page: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases 1. Can this cause my project to malfunction ? 2. What are the benefits of using this Python script ?
  11. I tried it with 2018.2 and got EXACTLY the same problem.
  12. Thanks. I'll try it with 2018.2 Meanwhile. I managed to workaround the problem by accessing manually changing the HDL inside file: system_MIPI_CSI_2_RX_0_0.vhd Which is located in: C:\Zybo-Z7-20-pcam-5c-2017.4-1\src\bd\system\ip\system_MIPI_CSI_2_RX_0_0\synth\system_MIPI_CSI_2_RX_0_0.vhd
  13. Hi, 1. If you downloaded the 2017.4 project version from GIT - and tried to compile it in the same version - why did it ask for an IP upgrade ? 2. Did you try to un-check the "Debug Module" box for the MIPI CSI-2 and re-compile ? Did it work ?
  14. Hello, I'm trying to modify the pcam-5c design for the Zybo board (Vivado 2017.4). The design takes up a lot of logic for debug especially in MIPI_CSI2_Rx.vhd. I tried removing this logic by un-checking the "Debug Module" box of the "MIPI CSI-2 Receiver" core inside the supplied block design. I saved the design and re-run synthesis - which failed with the following message : Re-checking the "Debug Module" box are re-synthesizing didn't solve the problem. The only thing that fixed the problem is copying the \src\bd\system\ip\system_MIPI_CSI_2_RX_0_0 folder from a mirror ( untouched ) design. 2 questions: 1. How did un-checking the "Debug Module" box cause the design to break in such irreversible way? 2. How can I reliably remove the ILA debug logic ?