yildizberat

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  1. Heyyy, problem was my monitor connector. Thanks for your helps @JColvin. and sorry to take your time. I am very happy now. I added solved this topic. Best regards.
  2. Hi @JColvin I downloaded 2018.2 and i ran https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/releases project. But same my monitor say "cable not connected". Also same monitor and same vga cable working with my pc via hdmi-vga converter. Some monitor settings at attachtments. I added Zybo Z7-10 board files and i didnt change anything on demo projects. But still not working. Maybe i have to send some signals to monitor for detect cable connection. I'm about to give up Maybe my pmod or board have some problems. thanks
  3. Hi @JColvin firstly, thanks for your response. I use Vivado 2019.1 and my monitor resolution is 1920x1080 resolution. My monitor information is : AOC E2350SAK 23" 5ms Inputs: D-SUB 1920 x 1080 maximum resolution Special Features: -5/15 Tilt,5:4 switch,Black glossy,DCB,Eco Mode,e-Saver,i-Menu,Kensington Security Lock,Low-Power,Off Timer,screen+,VESA 75 mm 250 cd/m² 5 ms Also now i am starting to download 2018.2 version for check if problem about vivado version. Also do you have any other idea? Thanks
  4. Hi friends, I am not senior at fpga. But i try to run vga on my board by digilent pmod vga demo. But not working so i dont understand why. please help me. My constraint file : ## This file is a general .xdc for the Zybo Z7 Rev. B ## It is compatible with the Zybo Z7-20 and Zybo Z7-10 ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project #Clock signal set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports sys_clock] create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports sys_clock] ###Switches #set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] #set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] #set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {sw[2]}] #set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {sw[3]}] ##Buttons #set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {btn[0]}] #set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {btn[1]}] #set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {btn[2]}] #set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {btn[3]}] #LEDs #set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {led[0]}] #set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {led[1]}] #set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {led[2]}] #set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {led[3]}] ##RGB LED 5 (Zybo Z7-20 only) #set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r #set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g #set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b ##RGB LED 6 #set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports led6_r] #set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b ##Audio Codec #set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat #set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat #set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc #set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda ##Additional Ethernet signals #set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b #set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b ##USB-OTG over-current detect pin #set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc ##Fan (Zybo Z7-20 only) #set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu ##HDMI RX #set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd #set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl #set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda #set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n #set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p #set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0] #set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0] #set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1] #set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1] #set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2] #set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2] ##HDMI RX CEC (Zybo Z7-20 only) #set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec ##HDMI TX #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd #set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda #set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n #set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p #set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0] #set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0] #set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1] #set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1] #set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2] #set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2] ##HDMI TX CEC #set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec ##Pmod Header JA (XADC) #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P #set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N #set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N #set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N #set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N ##Pmod Header JB (Zybo Z7-20 only) #set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1] #set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1] #set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2] #set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2] #set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3] #set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3] #set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4] #set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4] ##Pmod Header JC set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports { VGA_R[0] }] set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports { VGA_R[1] }] set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1P_T0_34 Sch=jc_p[2] set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L1N_T0_34 Sch=jc_n[2] set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L8P_T1_34 Sch=jc_p[3] set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L8N_T1_34 Sch=jc_n[3] set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L2P_T0_34 Sch=jc_p[4] set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L2N_T0_34 Sch=jc_n[4] #Pmod Header JD set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L5P_T0_34 Sch=jd_p[1] set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L5N_T0_34 Sch=jd_n[1] set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L6P_T0_34 Sch=jd_p[2] set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2] set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS_O }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3] set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS_O }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3] #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4] #set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4] ##Pmod Header JE #set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1] #set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2] #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3] #set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4] #set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7] #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8] #set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9] #set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10] ##Pcam MIPI CSI-2 Connector ## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk #create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p] #set_property INTERNAL_VREF 0.6 [get_iobanks 35] #set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n #set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p #set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0] #set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0] #set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1] #set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1] #set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n #set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p #set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0] #set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0] #set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1] #set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1] #set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk #set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio #set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl #set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda ##Unloaded Crypto Chip SWI (for future use) #set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda ##Unconnected Pins (Zybo Z7-20 only) #set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13 #set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13 #set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13 #set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13 #set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13 #set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13 #set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13 #set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13 #set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13 #set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13 #set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13 #set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13 my top module : ---------------------------------------------------------------------------------- -- Company: Digilent -- Engineer: Arthur Brown, Sam Bobrowicz -- -- -- Create Date: 13:01:51 02/15/2013 -- Project Name: pmodvga -- Tool versions: 2016.4 -- Additional Comments: -- -- Copyright Digilent 2017 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top is Port ( sys_clock : in STD_LOGIC; VGA_HS_O : out STD_LOGIC; VGA_VS_O : out STD_LOGIC; VGA_R : out STD_LOGIC_VECTOR (3 downto 0); VGA_B : out STD_LOGIC_VECTOR (3 downto 0); VGA_G : out STD_LOGIC_VECTOR (3 downto 0)); end top; architecture Behavioral of top is component clk_wiz_0 port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic ); end component; --Sync Generation constants --***1920x1080@60Hz***-- Requires 148.5 MHz pxl_clk constant FRAME_WIDTH : natural := 1920; constant FRAME_HEIGHT : natural := 1080; constant H_FP : natural := 88; --H front porch width (pixels) constant H_PW : natural := 44; --H sync pulse width (pixels) constant H_MAX : natural := 2200; --H total period (pixels) constant V_FP : natural := 4; --V front porch width (lines) constant V_PW : natural := 5; --V sync pulse width (lines) constant V_MAX : natural := 1125; --V total period (lines) constant H_POL : std_logic := '1'; constant V_POL : std_logic := '1'; --Moving Box constants constant BOX_WIDTH : natural := 8; constant BOX_CLK_DIV : natural := 1000000; --MAX=(2^25 - 1) constant BOX_X_MAX : natural := (512 - BOX_WIDTH); constant BOX_Y_MAX : natural := (FRAME_HEIGHT - BOX_WIDTH); constant BOX_X_MIN : natural := 0; constant BOX_Y_MIN : natural := 256; constant BOX_X_INIT : std_logic_vector(11 downto 0) := x"000"; constant BOX_Y_INIT : std_logic_vector(11 downto 0) := x"190"; --400 signal pxl_clk : std_logic; signal active : std_logic; signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); signal h_sync_reg : std_logic := not(H_POL); signal v_sync_reg : std_logic := not(V_POL); signal h_sync_dly_reg : std_logic := not(H_POL); signal v_sync_dly_reg : std_logic := not(V_POL); signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0'); signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0'); signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0'); signal vga_red : std_logic_vector(3 downto 0); signal vga_green : std_logic_vector(3 downto 0); signal vga_blue : std_logic_vector(3 downto 0); signal box_x_reg : std_logic_vector(11 downto 0) := BOX_X_INIT; signal box_x_dir : std_logic := '1'; signal box_y_reg : std_logic_vector(11 downto 0) := BOX_Y_INIT; signal box_y_dir : std_logic := '1'; signal box_cntr_reg : std_logic_vector(24 downto 0) := (others =>'0'); signal update_box : std_logic; signal pixel_in_box : std_logic; begin clk_div_inst : clk_wiz_0 port map (-- Clock in ports CLK_IN1 => sys_clock, -- Clock out ports CLK_OUT1 => pxl_clk); ---------------------------------------------------- ------- TEST PATTERN LOGIC ------- ---------------------------------------------------- vga_red <= h_cntr_reg(5 downto 2) when (active = '1' and ((h_cntr_reg < 512 and v_cntr_reg < 256) and h_cntr_reg(8) = '1')) else (others=>'1') when (active = '1' and ((h_cntr_reg < 512 and not(v_cntr_reg < 256)) and not(pixel_in_box = '1'))) else (others=>'1') when (active = '1' and ((not(h_cntr_reg < 512) and (v_cntr_reg(8) = '1' and h_cntr_reg(3) = '1')) or (not(h_cntr_reg < 512) and (v_cntr_reg(8) = '0' and v_cntr_reg(3) = '1')))) else (others=>'0'); vga_blue <= h_cntr_reg(5 downto 2) when (active = '1' and ((h_cntr_reg < 512 and v_cntr_reg < 256) and h_cntr_reg(6) = '1')) else (others=>'1') when (active = '1' and ((h_cntr_reg < 512 and not(v_cntr_reg < 256)) and not(pixel_in_box = '1'))) else (others=>'1') when (active = '1' and ((not(h_cntr_reg < 512) and (v_cntr_reg(8) = '1' and h_cntr_reg(3) = '1')) or (not(h_cntr_reg < 512) and (v_cntr_reg(8) = '0' and v_cntr_reg(3) = '1')))) else (others=>'0'); vga_green <= h_cntr_reg(5 downto 2) when (active = '1' and ((h_cntr_reg < 512 and v_cntr_reg < 256) and h_cntr_reg(7) = '1')) else (others=>'1') when (active = '1' and ((h_cntr_reg < 512 and not(v_cntr_reg < 256)) and not(pixel_in_box = '1'))) else (others=>'1') when (active = '1' and ((not(h_cntr_reg < 512) and (v_cntr_reg(8) = '1' and h_cntr_reg(3) = '1')) or (not(h_cntr_reg < 512) and (v_cntr_reg(8) = '0' and v_cntr_reg(3) = '1')))) else (others=>'0'); ------------------------------------------------------ ------- MOVING BOX LOGIC ------ ------------------------------------------------------ process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (update_box = '1') then if (box_x_dir = '1') then box_x_reg <= box_x_reg + 1; else box_x_reg <= box_x_reg - 1; end if; if (box_y_dir = '1') then box_y_reg <= box_y_reg + 1; else box_y_reg <= box_y_reg - 1; end if; end if; end if; end process; process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (update_box = '1') then if ((box_x_dir = '1' and (box_x_reg = BOX_X_MAX - 1)) or (box_x_dir = '0' and (box_x_reg = BOX_X_MIN + 1))) then box_x_dir <= not(box_x_dir); end if; if ((box_y_dir = '1' and (box_y_reg = BOX_Y_MAX - 1)) or (box_y_dir = '0' and (box_y_reg = BOX_Y_MIN + 1))) then box_y_dir <= not(box_y_dir); end if; end if; end if; end process; process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (box_cntr_reg = (BOX_CLK_DIV - 1)) then box_cntr_reg <= (others=>'0'); else box_cntr_reg <= box_cntr_reg + 1; end if; end if; end process; update_box <= '1' when box_cntr_reg = (BOX_CLK_DIV - 1) else '0'; pixel_in_box <= '1' when (((h_cntr_reg >= box_x_reg) and (h_cntr_reg < (box_x_reg + BOX_WIDTH))) and ((v_cntr_reg >= box_y_reg) and (v_cntr_reg < (box_y_reg + BOX_WIDTH)))) else '0'; ------------------------------------------------------ ------- SYNC GENERATION ------ ------------------------------------------------------ process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (h_cntr_reg = (H_MAX - 1)) then h_cntr_reg <= (others =>'0'); else h_cntr_reg <= h_cntr_reg + 1; end if; end if; end process; process (pxl_clk) begin if (rising_edge(pxl_clk)) then if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then v_cntr_reg <= (others =>'0'); elsif (h_cntr_reg = (H_MAX - 1)) then v_cntr_reg <= v_cntr_reg + 1; end if; end if; end process; process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then h_sync_reg <= H_POL; else h_sync_reg <= not(H_POL); end if; end if; end process; process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then v_sync_reg <= V_POL; else v_sync_reg <= not(V_POL); end if; end if; end process; active <= '1' when ((h_cntr_reg < FRAME_WIDTH) and (v_cntr_reg < FRAME_HEIGHT))else '0'; process (pxl_clk) begin if (rising_edge(pxl_clk)) then v_sync_dly_reg <= v_sync_reg; h_sync_dly_reg <= h_sync_reg; vga_red_reg <= vga_red; vga_green_reg <= vga_green; vga_blue_reg <= vga_blue; end if; end process; VGA_HS_O <= h_sync_dly_reg; VGA_VS_O <= v_sync_dly_reg; VGA_R <= vga_red_reg; VGA_G <= vga_green_reg; VGA_B <= vga_blue_reg; end Behavioral; Also : You can see my clock wizard configration and my connection pmod to board at attachments. I hope i can resolve this problem via your helps. Best regards.