satvik

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  1. Hello @Ana-Maria Balas Thank you so much for your reply and i am happy to say that i got sollution for my problem. i got the actual problem in my case is, i connected my IP core to Zynq SOC clock out (FCLK_CLK0) but i was uploading the bit file from vivado Hardware Manager and expect to get output without running any application form SDK. When i run application from SDK then only the FCLK_CLK0 give clock out and my own IP core(PmodDAC2) give me output. Now same thing happen with custom axi ip core and i got my problem solved. Thank you for your suggestions. I have gone throgh all links that you provided and it is quit helpfull to me.
  2. Hello @[email protected] and @zygot Sorry for late reply and thank you somuch for your support as always you did. Finally i got the actual problem in my case is, i connected my IP core to Zynq SOC clock out (FCLK_CLK0) but i was uploading the bit file from vivado Hardware Manager and expect to get output without running any application form SDK. When i run application from SDK then only the FCLK_CLK0 give clock out.
  3. @[email protected], Thank you @[email protected] and @zygot If there is no bug and error then why my led is continuously stay ON, its like no effect of button press. If I put only "assign led = button;" instead of always block it works fine. What is the reason behind that?
  4. Hello everyone, I am working on CoraZ0S Zynq Block design with Pmod DAC. I successfully run my SPI Verilog interface for Pmod DAC and i got ramp up signal from Pmod DAC. I make IP core from that code. I started new block design and add only my SPI IP core for Pmod DAC and make clock and output as extern and assign pin and run on my board again it give ramp up signal. I want to connect my IP core with ZYNQ SOC IP core because I want to get data from ARM whichi will pass to PmodDAC via my SPI IP core. I add ZYNQ ip core and connect my SPI IP core clock signal to FCLK_0(set to 100Mhz) of ZYNQ IP core and rest of left as it is. Then I generate bit/ bin file and load on my board but there is no output form Pmod DAC. After that i generate test bench and in simulation output is apear from my SPI IP core. Then why no output when i load onto FPGA board. Is there any mistake i did or i miss any step? Thansk in advance.
  5. Hellow @[email protected], Thank you for valuable reply and i am following your all previous comments. I accept all your suggestion and i want to say that i put my led login in file TestDAC3_v1_0.V if you can check it. I apologize to attache my old version IP core project buti will follow your suggestion and try with axi-lite. My aim is to get data from ARM processor to FPGA and then pass it to PmodeDAC using my spi logic. Now I successfully test ramp up signal on PmodeDAC and pack that verilog code in IP core. Once again i creat new block design and put only my PmodeDAC IP core(no AXI only pure SPI core of mine) connect external clock and pmode pins and it work fine on my board. But i need to connect it with zynq soc ip so i added zynq soc ip and connect my ip core's clk pin to zynq FCLK_0(set 100Mhz) pin and genratebit stream successfully. When i load my board theni got nothing on that PmodeDAC. Is ther any working code with tutorial which send data from ARM to FPGA IP core and process in fPGA and send to physical pin even on board led or something similar. I really really need help in this. I will upload my pmodeDAC. Once again thank you so much
  6. Thank you, supporters in advance. I am working on Custom Axi slave IP core on ZYNQ based digilent Cora-Z0S board in vivado 2018.2. I successfully have done its example and add my own logic which is working fine with ARM and I can receive data in ARM(C code). After that, I connect my IP core to the external port like led(onboard) and some physical pins for my external DAC module. I added the ports into custom IP Verilog code according to my design and it appears in GUI as well. Then I connect that custom IP to ZYNQ in block design and make those led and other ports as extern by right click on it and assign the pin number using pin layout. I got successfully generated the bit-stream. The problem starts when I upload the bit-stream on board then I am not getting any output on any pin. the led consciously blow if I assign 1'b1 to it in initialize block. I made all output including led as register. Then I include onboard button and using assign statement assign button value to led(change reg to wire) then only it works but it is not working when I use led(change back to reg) and button in always block and apply button value to led (led <= button;). I generate test-bench and in that, I am getting all value on all ports the same as my desire but not from board physical pins. I attached the custom AXI IP core vivado project(DacTestIP.rar). Please help me. I am wondering what mistake am I making? DacTestIP.rar
  7. Hello @JColvin, Thank you for your reply. I have seen all those examples and i am successfully using pmodeWifi with my Zedboard by one of your post also i developed additional functionalities using C/C++ in SDK . I have develop my own network and communicate between Zedboard, Desktop(with Wifi adepter) and Android device. Recently i orderd Cora z7 and pmodeESP32. Usally i test my design before i ordere board but in Cora z7 after i ordered i come to know that i have to select Cora z0-7s board instead of Cora Z-10 but you give me the correct solution. so that is very helpful for me Apart from that i want some more infromation about PmodeWifi Send and Receive Time calculation live example because in one of my research project i have to send 5000 bytes within 10ms or less. I know the pmodeWifi standard datarate is 1 and 2 mbps but i need standard c or c++ code to validate speed. Thanks and ragards, Satvik Patel
  8. Hello @JColvin, Thank you somuch for your humble reply and appriciate for that. Actually I have nodelocked permanent licent of vivado but my licence Version limit is 2016.05. I have one question is if i use Cora z7-07s in webpack version of Vivado 2017.4 then i can use all its functionality? I mean i will going to add PmodeWifi to Cora z7-07s in design project and run my server on sd card so all that i can do with webpack version of vivado because i never used webpack since i had licence. Thanks and ragards, Satvik Patel
  9. Hello everyone, I am working on zynq FPGA systems and curruntly i start working on Cora z7-07s board but when i add board file in vivado 2015.4 of Cora z7-10 and Cora z7-07s then cora z7-10 is successfully recognize and i can see in boards tab but Cora z7-07s is not appear also i can not find the part XC7Z007S-1CLG400C in part tab. The screenshot is attached. While installing Vivado i make sure that i select zynq 7000 series part to install. Even i install vivado 2016.1 but same problem in that also.
  10. Hello @JColvin, I have same type of problem but in my vivado 2015.4 Cora Z7-10 is showing but Cora Z7-07S is not appear even i selected the zynq 7000 chip while installation still the xcz007s part also not appear. Thanks and Regard satvik