satvik

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  1. thank you @jpeyron for showing me the problem and i will work on it first thing i will restrict my file name to 8 character. then i will look for the code to find the solution.
  2. Hi @thinkthinkthink, Can you share any example like: large data communication, HTTP web server, TCP/udp Server/client of esp32 using zynq?
  3. Thank you so much @thinkthinkthink,this helps me a lot and i have to add one thing before send any commands i have to press BTN1 of esp32 module otherwise it won't reply anything.
  4. Hello @Bianca I am using ZedBoard REV D (D657476) by digilent. I also attached my block design and SDK esp32 example demo code Response photos.
  5. Hi @jpeyron, I added the Pmode ESP32 IP with zynq and it compile and open SDK but when i execute ESP32 example demo to work with AT command from zedboard usb-uart then i receive "AT" in response to "AT". Whatever i type and send i receive same text back. I can not receive ok response from ESP32. I have done the same block diagram as StefanOR did and i did not receive any error or warning. I have tried two functions (1)void ESP32_HardwareEnable(PmodESP32 *InstancePtr); (2)void ESP32_HardwareDisable(PmodESP32 *InstancePtr); to check wether my esp32 working or not but it is working and i can
  6. Hello Everyone, I am working in PmodeWiFi on Zedboard example HTTP and I modify to read file names on SD card directory and it's working but File name read by code is not completely correct. I have included the screenshot of code as well as output in attachment with modified files of example HTTP. Kindly guide me if i have done any mistake in coding. Thanks in advance Satvik DFATFS.cpp DFATFS.h HTMLSDPage.cpp
  7. Hello @Ana-Maria Balas Thank you so much for your reply and i am happy to say that i got sollution for my problem. i got the actual problem in my case is, i connected my IP core to Zynq SOC clock out (FCLK_CLK0) but i was uploading the bit file from vivado Hardware Manager and expect to get output without running any application form SDK. When i run application from SDK then only the FCLK_CLK0 give clock out and my own IP core(PmodDAC2) give me output. Now same thing happen with custom axi ip core and i got my problem solved. Thank you for your suggestions. I have gone t
  8. Hello @[email protected] and @zygot Sorry for late reply and thank you somuch for your support as always you did. Finally i got the actual problem in my case is, i connected my IP core to Zynq SOC clock out (FCLK_CLK0) but i was uploading the bit file from vivado Hardware Manager and expect to get output without running any application form SDK. When i run application from SDK then only the FCLK_CLK0 give clock out.
  9. @[email protected], Thank you @[email protected] and @zygot If there is no bug and error then why my led is continuously stay ON, its like no effect of button press. If I put only "assign led = button;" instead of always block it works fine. What is the reason behind that?
  10. Hello everyone, I am working on CoraZ0S Zynq Block design with Pmod DAC. I successfully run my SPI Verilog interface for Pmod DAC and i got ramp up signal from Pmod DAC. I make IP core from that code. I started new block design and add only my SPI IP core for Pmod DAC and make clock and output as extern and assign pin and run on my board again it give ramp up signal. I want to connect my IP core with ZYNQ SOC IP core because I want to get data from ARM whichi will pass to PmodDAC via my SPI IP core. I add ZYNQ ip core and connect my SPI IP core clock signal to FCLK_0(set to 100Mhz) o
  11. Hellow @[email protected], Thank you for valuable reply and i am following your all previous comments. I accept all your suggestion and i want to say that i put my led login in file TestDAC3_v1_0.V if you can check it. I apologize to attache my old version IP core project buti will follow your suggestion and try with axi-lite. My aim is to get data from ARM processor to FPGA and then pass it to PmodeDAC using my spi logic. Now I successfully test ramp up signal on PmodeDAC and pack that verilog code in IP core. Once again i creat new block design and put only my PmodeDAC IP core(no AXI onl
  12. Thank you, supporters in advance. I am working on Custom Axi slave IP core on ZYNQ based digilent Cora-Z0S board in vivado 2018.2. I successfully have done its example and add my own logic which is working fine with ARM and I can receive data in ARM(C code). After that, I connect my IP core to the external port like led(onboard) and some physical pins for my external DAC module. I added the ports into custom IP Verilog code according to my design and it appears in GUI as well. Then I connect that custom IP to ZYNQ in block design and make those led and other ports as extern by
  13. Hello @JColvin, Thank you for your reply. I have seen all those examples and i am successfully using pmodeWifi with my Zedboard by one of your post also i developed additional functionalities using C/C++ in SDK . I have develop my own network and communicate between Zedboard, Desktop(with Wifi adepter) and Android device. Recently i orderd Cora z7 and pmodeESP32. Usally i test my design before i ordere board but in Cora z7 after i ordered i come to know that i have to select Cora z0-7s board instead of Cora Z-10 but you give me the correct solution. so that is very helpful for me
  14. Hello @JColvin, Thank you somuch for your humble reply and appriciate for that. Actually I have nodelocked permanent licent of vivado but my licence Version limit is 2016.05. I have one question is if i use Cora z7-07s in webpack version of Vivado 2017.4 then i can use all its functionality? I mean i will going to add PmodeWifi to Cora z7-07s in design project and run my server on sd card so all that i can do with webpack version of vivado because i never used webpack since i had licence. Thanks and ragards, Satvik Patel