# sab

Members

6

1. ## Power utilization frequency

Thanks. I have a few more questions... What does "Worst Negative slack" represent? I know it has to be positive, but... for example, for my Artix target, I got 3.96 ns, for Kintex, 5.421 ns and for Spartan, 4.023 ns. Since I'm making a comparison which one would be better? Also, I'm to determine the maximum frequency... I found out that it would be the inverse of the time values. So, I get for Artix, 252.252 MHz; 184.467 MHz for Kintex and 248.570 MHz for Spartan. Which one is better and how can I interpret it? I first fell like the highest the frequency was, the better (because it might represent the speed of the device(?)) but now I'm not sure. I've read very different things about it online... Thanks.
2. ## Power utilization frequency

@[email protected] Thank you but sorry, I really don't know. I'm not familiar with that, I just learned how to program in VHDL and that's about it. I'm right now learning a little bit more through this exercise. @zygot What's BRAM (I read online block RAM?) and how can I check about BRAM for my design? Anyway, thank you. A lot of helpful infos.
3. ## Power utilization frequency

@zygot I wrote what I was asked: to make a power and resources study... and then compare them for the implementation on an artix, kintex, spartan (and something else that I forgot) chip. And finally tell how I can improve my design. First of all, I need to understand what each value really means for my design and I'll see how I can improve it later. I seriously can't explain more because I said everything that I was told...
4. ## Power utilization frequency

@JColvin Thank you for the reply. I actually guessed for FF (:)) but I don't know how to analyze the numbers, I don't know what is good or bad. @[email protected], Thank you for the reply. The filter response has 16 elements (actually 32, but it's symmetrical, so only 16 elements are stored in that ROM). Yes the coefficients are fixed and have a width of 11 bits. The input data have a width of 12 bits and are stored in an array of 32 elements through a DPRAM; only after the 32 values are stored that the calculation begins. And of course the output data has a width of 23 bits. My design has a SAMPLER that samples the input signal, a DPRAM (with a port for writing and another for reading), a ROM (for the impulse response coefficients), a MULTIPLIER, an ACCUMULATOR, and a SEQUENCER (that manages the FSM for the whole design). Guys, how do you interpret the energy? Is 0.084 W good or bad as total power on-chip for the Kintex? And does anyone know the clock pin names for KINTEX (xc7k70tfbg484-1) and SPARTAN (xc7s6cpga196-1)? I saw online respectively G7 and A7 on xilinx website but each time the implementation shows a critical warning and says that it's "...not a valid site or package pin name". Thank you very much for all the replies.
5. ## Power utilization frequency

Hi everyone, I worked on a digital synthesis project and we were supposed to implement a FIR filter and then run the implementation and study the power consumption, resources utilization, frequency, etc. and I have never done that and I'm a bit lost. I'd like to know how interpret those data on the pictures. Please help me analyze those numbers and figures. (Also, it reads that my design uses 430 LUTs (at least I know what LUTs means), but isn't that number a little high? Is my design too... "heavy" or something? What about all the other numbers...?) Any help would be welcome. Thank you in advance. :)
6. ## no hardware found on vivado 2019.1

I have a problem, my vivado doesn't recognize the device. I recently downloaded vivado 2019.1 but I never have this problem with vivado 2018.3 until it stopped working. I'm no expert on the technicapart of vivado, I just know how to write a few codes from school and I'm trying to improve my school on a NEXYS A7 (ARTIX 100T CSG324), so please explain like you would do to a baby (lol). Thank you.