krjdev

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  1. Hi, I have noticed an issue in a bare-metal application when polling the register XUARTPS_ISR (Channel Interrupt Status Register). No issues when I use XUART_SR (Channel Status Register) instead. The issue: When I poll XUART_ISR for TX_FULL and RX_EMPTY the UART interface becomes an unstable state. No sending and receiving after a few bytes is possible. Has somebody noticed the same issue or can somebody explain whats happening? Edit: My current code for the UART interface (Here I use XUARTPS_SR instead. But when I poll XUARTPS_ISR (0x14) it doesn't work.): #include <string.h> #include <dev/io.h> #define UART0_BASE 0xE0000000 #define UART1_BASE 0xE0001000 #define UART_CR_OFFSET 0x0 #define UART_CR_RXRST 0 #define UART_CR_TXRST 1 #define UART_CR_RXEN 2 #define UART_CR_RXDIS 3 #define UART_CR_TXEN 4 #define UART_CR_TXDIS 5 #define UART_MR_OFFSET 0x4 #define UART_IER_OFFSET 0x8 #define UART_BGEN_OFFSET 0x18 #define UART_SR_OFFSET 0x2C #define UART_SR_RXEMPT 1 #define UART_SR_RXFULL 2 #define UART_SR_TXEMPT 3 #define UART_SR_TXFULL 4 #define UART_FIFO_OFFSET 0x30 #define UART_BDIV_OFFSET 0x34 struct uart_reg { unsigned int cr; unsigned int mr; unsigned int ier; unsigned int bgen; unsigned int sr; unsigned int fifo; unsigned int bdiv; }; static struct uart_reg regs; void uart_init(void) { unsigned int tmp; regs.cr = (UART1_BASE + UART_CR_OFFSET); regs.mr = (UART1_BASE + UART_MR_OFFSET); regs.ier = (UART1_BASE + UART_IER_OFFSET); regs.bgen = (UART1_BASE + UART_BGEN_OFFSET); regs.sr = (UART1_BASE + UART_SR_OFFSET); regs.fifo = (UART1_BASE + UART_FIFO_OFFSET); regs.bdiv = (UART1_BASE + UART_BDIV_OFFSET); /* Check if RX/TX is enabled */ tmp = io_rd32(regs.cr); /* Skip init if RX/TX enabled */ if (tmp & ((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN))) return; /* Reset RX/TX paths */ tmp = io_rd32(regs.cr); tmp |= ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST)); io_wr32(regs.cr, tmp); do tmp = io_rd32(regs.cr); while (tmp & ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST))); /* Set baudrate to 115200; UART Reference Clock: 100MHz */ io_wr32(regs.bgen, 124); io_wr32(regs.bdiv, 6); /* Set mode: 8 Databit, 1 Stopbit, No Parity */ io_wr32(regs.mr, 0x20); /* Enable RX/TX */ tmp = io_rd32(regs.cr); tmp &= ~((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN)); io_wr32(regs.cr, tmp); } int uart_send(unsigned char *buf, int len) { int i; unsigned int tmp; for (i = 0; i < len; i++) { do tmp = io_rd32(regs.sr); while (tmp & (1 << UART_SR_TXFULL)); io_wr08(regs.fifo, buf[i]); } return len; } int uart_recv(unsigned char *buf, int len) { int i; int ret = 0; unsigned int tmp; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return 0; for (i = 0; i < len; i++) { buf[i] = io_rd08(regs.fifo); ret++; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return ret; } return ret; }
  2. Hi @artvvb Okay, thanks. I have added these parameters. Now the "Connect board component" works. But I run into a new problem. I have created a unmanaged XDC (TCL) file for the IP. When I open the Top Level Design and execute the following TCL commands by hand, it works: synth_design source path/to/my_unmanaged_constraint.tcl opt_design place_design route_design write_bitstream But not in GUI. Vivado doesn't execute the file. I don't know how the set the properties from the file to get executed. Tried the following: Parameter: USED_IN_IMPLEMENTATION Process Order: EARLY
  3. Hi @JColvin, No problem. The jumper setting on JP6 what I use is pin VU5V0 to pin WALL. I have tried to switch a rectifier diode serial in the supply voltage. Now the board works fine. The voltage drop after the diode has helped. According to your technical reference manual, the maximum voltage should be 5.7V. I have measured the supply voltage with two different instruments (multimeter and oscilloscope). Both of them display only max. 5.5V from the external power supply. Edit: Currently I have no laboratory power supply at home. So I cannot test in which voltage range the board works.
  4. Hello, I want create a custom IP for the Pmod interface. A simple GPIO Interface as example. But I run into a problem. I have downloaded the vivado-library from Digilent and placed the interface folder in my project. The Pmod Interface is available under Vivado. I added these port definitions in the top VHDL file of the AXI peripheral: pmod_pin0_i : in std_logic; pmod_pin0_o : out std_logic; pmod_pin0_t : out std_logic; pmod_pin1_i : in std_logic; pmod_pin1_o : out std_logic; pmod_pin1_t : out std_logic; pmod_pin2_i : in std_logic; pmod_pin2_o : out std_logic; pmod_pin2_t : out std_logic; pmod_pin3_i : in std_logic; pmod_pin3_o : out std_logic; pmod_pin3_t : out std_logic; pmod_pin4_i : in std_logic; pmod_pin4_o : out std_logic; pmod_pin4_t : out std_logic; pmod_pin5_i : in std_logic; pmod_pin5_o : out std_logic; pmod_pin5_t : out std_logic; pmod_pin6_i : in std_logic; pmod_pin6_o : out std_logic; pmod_pin6_t : out std_logic; pmod_pin7_i : in std_logic; pmod_pin7_o : out std_logic; pmod_pin7_t : out std_logic; After that I selected Ports and Interfaces in Package IP window. Then I add a Pmod Interface and mapped the ports from the VHDL file with the Digilent Pmod Interface. I added Pmod to the description field. But when I repackage the IP and I try to click on Connect Board Component it doesn't work. What is missing? Thanks in advance!
  5. Hi, I'm new in this forum. Have an issue with the ZYBO-Z7 when I use an external power supply. The board doesn't power-up very often when I turn on the power switch (SW4). eFuse? The open circuit voltage from the power supply is between 5.45V and 5.50V. When the board is powered over USB, everything works fine.