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  1. Can confirm that commenting out the xdc files in component.xml resolves timing errors for DVI-to-RGB 1.9 IP Core with >120 MHz (1080p) configuration. Thanks for the help! <!-- <spirit:file> <spirit:name>src/ila_timing_workaround.xdc</spirit:name> <spirit:userFileType>xdc</spirit:userFileType> <spirit:userFileType>USED_IN_implementation</spirit:userFileType> <spirit:userFileType>USED_IN_synthesis</spirit:userFileType> <spirit:define> <spirit:name>processing_order</spirit:name> <spirit:value>late</spirit:value> </spirit:define> </spirit:file> <spirit:file> <spirit:name>src/dvi2rgb.xdc</spirit:name> <spirit:userFileType>xdc</spirit:userFileType> </spirit:file> <spirit:file> <spirit:name>src/dvi2rgb_ooc.xdc</spirit:name> <spirit:userFileType>xdc</spirit:userFileType> </spirit:file> -->
  2. So a workaround would be to remove the xdc file sets from the component.xml file?
  3. I ran into the same issue on the using the DVI-to-RGB 1.9 IP Core when building the Nexys HMDI example ( I tried building with Vivado 2017.4, and had to manually update DVI-to-RGB from 1.7 to 1.9 to point to the correct version in vivado-library ( Upon changing the resolution to >120 MHz (1080p), I am able to generate a bitfile. However, when reporting timing, the design fails to meet timing. I have included the timing report (timing1.txt), the WNS is -4.2 ns and the TNS is about -13,000 ns. I tried removing the debug ILA cores in DVI-to-RGB (debug off) to see if that helped timing, along with changing the implementation strategy with no luck. I was able to successfully build and test the project from this release using Vivado 2018.2 and DVI-to-RGB 1.7 IP Core: - Configured for < 120 MHz Not sure how else to troubleshoot these timing errors on DVI-to-RGB 1.9 and >120 MHz (1080p) timing1.txt