petera

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  1. Nexsys Video - Vivado 2019.1.3 Nexys-Video-GPIO-2016.4-1.zip\Nexys-Video-GPIO\proj - ZIP archive, unpacked size 171,041 bytes Nexys-Video-GPIO-2016.4-1.zip
  2. – NEXSYS VIDEO – 10 errors on first pass – IP out of sync – too old??? Name Severity Details Vivado Commands General Messages Common 17-70 Error Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s): charLib_synth_1 init_sequence_rom_synth_1 pixel_buffer_synth_1 These failed run(s) need to be reset prior to launching 'impl_1' again. Synthesis Out-of-Context Module Runs charLib_synth_1 Synth 8-439 Error module 'charLib' not found Common 17-69 Error Command failed: Synthesis failed - please see the console or run log file for details init_sequence_rom_synth_1 Synth 8-439 Error module 'init_sequence_rom' not found Common 17-69 Error Command failed: Synthesis failed - please see the console or run log file for details pixel_buffer_synth_1 Synth 8-439 Error module 'pixel_buffer' not found Common 17-69 Error Command failed: Synthesis failed - please see the console or run log file for details This is the way its supposed to work…… 1. Download the Project ZIP from the Digilent Github This step describes how to download a release from the Digilent Github, you can alternatively just download the project archive directly by clicking the link in the Projects Supported table above. The archive can be placed wherever you want, and will need to be extracted with Right click → Extract All. Download from Github 2. Open the Project Select the “SDK Hardware Handoff” option if your project supports Vivado SDK and you want to jump directly in, otherwise select the “Vivado” option. Review the Supported Projects table above to determine if the project is an SDK project. SDK Hardware Handoff Vivado 3. Generate Bitstream Skip this step if you previously selected the “SDK Hardware Handoff” option. Generate Bitstream 3.1) Click Generate Bitstream on the left hand menu towards the bottom. In the “Launch Runs” dialog, make sure Launch runs on local host is selected and click OK. In the “No Implementation Results Available” dialog, click Yes to run synthesis and implementation. Tip If your computer has multiple CPU cores, you can increase the number of jobs to make this process faster. 3.2) When this process has finished, which may take a while, in the “Bitstream Generation Completed” dialog you will be presented with several options. You can Open Implemented Design to view how your design will be placed onto the FPGA. View Reports will show you a number of different diagnostics on your project, including how the resources of your board will be used. Open Hardware Manager is used to program the bitstream onto the board (this will not be used for the SDK flow). Generate Memory Configuration File creates a file that can be used to program the bitstream from local memory on your device. Thank you, Peter Ateshian, Xtrm Designs LLC peter.ateshian@espsafetyinc.com prateshi@gmail.com 415-470-1008