Rodrigo_Montero

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About Rodrigo_Montero

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  1. Hello, Im working on the following IP Integrator design. I have an Arty7 35T FPGA I want to create a block diagram with two modules. The objetive for this implementation is to create a Analog-Digital-Analog vivado project (This one will be a part for a big project). The modules are: - XADC: Input 0-3.33v converted to 16bits. This one as a clock input ( CLK100MHZ ) - Pmod DA3: Digital to Analog converter with SPI Protocol. Inputs 16bits is converted by SPI protocol in a Analog value (max 2.51v). This one as a clock input ( i_clk ) My first idea was to connect