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  1. Hi @JColvin, I have been using the Embedded Vision Bundle and successfully modified the project as well. Can you help me understand how to find or know the processing time taken by each filter? Thanks
  2. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does typename P_T mean and how to define it in the header file. I am getting the following error with the current code that I have written C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h: In function 'void hls::Range(hls::Mat<ROWS, COLS, SRC1_T>&, hls::Mat<ROWS, COLS, SRC2_T>&, P_T, P_T) [with int ROWS = 720, int COLS = 1280, int SRC_T = 4096, int DST_T = 4096, P_T = hls::Scalar<3, unsigned char>]': ../../../yellow_threshold.cpp:24:32: instantiated from here C:/xilinx/Vivado/2017.4/include/hls/hls_video_arithm.h:1042:22: error: conversion from 'hls::Scalar<3, unsigned char>' to non-scalar type 'hls::_AP_T {aka ap_fixed<64, 32, (ap_q_mode)0u>}' requested make: *** [obj/yellow_threshold.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s) Please find the attached files for more details and suggest me how can I proceed. Thanks yellow_threshold.cpp yellow_threshold.h
  3. Hi, I am using the Embedded Vision Demo project for Image processing. I created a new filter by creating a new IP core for it in Vivado HLS 2017.4 (for the first time) referring to the filters used in the demo and then exported it. I added the new IP in the Embedded Vision Demo in Vivado 2017.4 and made the required connections followed by generating the block design. I was able to successfully complete all these tasks, however when I try to run the demo using Xilinx SDK 2017.4 (the same way I ran the demo prior to adding new filter) it does not read the switch change in hardware for this new filter thus not showing any results for it. The already present filters work in the same way as before. I am new to working with Xilinx SDK and Vivado HLS, kindly guide me if I am doing anything wrong and suggest me if any changes are to be done in the SDK files. bd.pdf
  4. I was able to run the demo successfully. . Thank you so much for the detailed information @JColvin
  5. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20 pcam 5c for this demo as well). Kindly guide me with the steps to be followed in order to get the demo working. Reference manual : https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.170407588.585429254.1575373921-868278974.1575373921 Thanks. EmbeddedVisionDemo.pdf
  6. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current version. After the project opens, there is another pop-up to Report IP, I tried both the options individually i.e. Report IP and Ignore. It did not give any error in any of the following steps. But, the screen displays just a moving colour pattern and I am not able to communicate to camera module via UART as suggested in the demo. To summarise, all the steps mentioned in the demo were performed but the camera module is not working. I am unable to see the UART communication channel. I also tried following the instructions to use digilent github demo projects: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start However, this uses the 2016.4 version. I used the SDK Handoff method and again faced the same problem. Kindly suggest possible solutions to make this demo work on 2019.1 version or tell me what have I been doing wrong. Thanks.