V94

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  1. Hi, I want to create a test pattern generator project that uses the TPG IP to display the test patterns on the monitor via HDMI. For this I have been referring the Xilinx Video Series 19, however, the hardware used in the video is ZC702 and the hardware I am using is Zybo Z7-10. I also checked the HDMI demo available for Zybo Z7-10 but it does not include the TPG IP. Kindly suggest how can I achieve the same. I tried to replicate the block design from the video series 19 and made a few changes but I am not sure about it and got a few errors. I have attached the block diagram image an
  2. Hi @JColvin, I have been using the Embedded Vision Bundle and successfully modified the project as well. Can you help me understand how to find or know the processing time taken by each filter? Thanks
  3. Hello, I am working on video processing using Z7-20 Pcam 5c, for this I have created an IP block which converts rgb image to hsv. Now, I want to filter it to obtain only the yellow color. So for this I am trying to use the hls::range function to threshold the pixels in the range of yellow color. As per the manual, the template is as follows: template<int ROWS, int COLS, int SRC_T, int DST_T, typename P_T> void hls::Range ( hls::Mat<ROWS, COLS, SRC_T>& src, hls::Mat<ROWS, COLS, DST_T>& dst, P_T start, P_T end); I want to understand what does ty
  4. Hi, I am using the Embedded Vision Demo project for Image processing. I created a new filter by creating a new IP core for it in Vivado HLS 2017.4 (for the first time) referring to the filters used in the demo and then exported it. I added the new IP in the Embedded Vision Demo in Vivado 2017.4 and made the required connections followed by generating the block design. I was able to successfully complete all these tasks, however when I try to run the demo using Xilinx SDK 2017.4 (the same way I ran the demo prior to adding new filter) it does not read the switch change in hardware for this
  5. I was able to run the demo successfully. . Thank you so much for the detailed information @JColvin
  6. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20
  7. Hello, I have been trying for a while to run this PCAM 5c demo example that is provided by Digilent on a Zybo z7-20 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c The demo uses Vivado 2018.2 version, however I have been trying to execute it on the 2019.1 version. I am very new to FPGA and VHDL. I followed all the steps mentioned in the demo perfectly and did not receive any error. Although, after opening the project in the 3rd step, a pop-up window informs that the project is of the older version and I checked the option of automatically upgrading the project to current v