amitceder

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  1. seems the gui was stuck on a jtag sampling loop. after rebooting the pc it stopped and sampled correctly the ip as cpld unknown. platform is vcu118 and zcu104. but it behave d the same prior to rebooting
  2. only a platform for the jtag supported ip. of course i did not intend to program the fpga with it. please read again and respond
  3. hi i baught 2 hs3 programmer and getting the same results. trying to connect to a jtag supported ip i fail to initialize with adept latest gui. i am able to enumarate. i see input and output signals on chipscope of the jtag ports toggle according to a golden sequence. the platform is xilinx ultrascale plus based and connected with jumper wires from the hs3 to pmod connector on the xilinx eval board. at first i found a mirror in the hs3 pinout on digilent website. once realized that the verf is corrected and all signals in chipscope appear as discussed above. any ideas what can still fail the init of adept?