Luke Abela

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  1. Good day, I have an issue regarding integration of .VHD files in a format of hierarchal VHDL. I have written an LVDS DDR reception protocol in VHDL, and have done a behavioural simulation and a post-implementation timing simulation of this file. Both simulations returned the intended results. I then went to call this LVDS file from a TOP file. I assigned physical inputs (NEXYS4DDR) to connect to my LVDS protocol, and assigned the output to test LEDs and ILA (my intention is to set and see a repeated digital word receieved and output), however, when I ran the post-implementation timing simulation with the top file, my results were altered (my behavioural simulation of top file was successful). Has anyone ever encountered a similar issue? Any and all help welcome. Regards, Luke
  2. At the crux of it all, we`re talking about simulations with varying levels of details in regards to their considerations. I have attempted an alternate design which does not require timing constraints from the wizard in order to meet its timing requirements, however, I am still reaching the same issue regarding a mismatch in my simulation results. I have also spent time with the previous iteration fiddling with constraint parameters and was met with little reward. I don`t suppose there any obvious of generic approaches to fixing this issue. I have struggled to find comprehensive literature or guidance regarding such discrepancies... perhaps I`m not looking correctly?
  3. The design I`m working involved high speed digital signals to the tune of 400 MHz, so what you are suggesting that routing delays may be an issue definitely sounds likely. My question now is how should I alter my design in order to accommodate such issues? Is it a matter of using the constraints wizard, or rather, will I have to manually configure which CLBs are used and which aren`t?
  4. Good day, I would like to enquire regarding the Vivado 2018.3 simulation tools. I typically use the behavioural simulation in order to verify my logic, however, I recently attempted using the post-implementation timing simulation and was met with significantly different results. Could someone kindly breakdown what may lead to such an outcome? Thank you and regards, Luke Abela
  5. Good day, I am currently creating a relatively large FPGA project. The main architecture is that I will have a number of hardware based VHDL files controlled by a soft-core microblaze IP. Using this microblaze controller I have also created an echo server as per Xilinx`s Nexys 4 DDR echo server tutorial. My question pertains to the structural VHDL required: Should I create a top file, and call the design wrapper from that top file, in which case, to where should I map the externalised DDR2 signal ports? Alternatively, Should I use the design wrapper as my top, and simply call my external VHDL files from the wrapper`s VHDL file? Thank you and regards, Luke
  6. Good day, I am currently working on a system which requires ethernet control on an FPGA. To this extent I have successfully managed to implement the echo server as per Xilinx`s tutorial. However, I now require to transmit data from my laptop to the FPGA. I am unsure of how to amend this project in its current state to receive data from an external program (such as matlab) and from where to verify the data I have received is correct. Could anyone kindly provide some insight? Regards
  7. Good Day, I have followed the Nexys 4 DDR tutorial - getting started with microblaze servers: I have however run into an issue. I have managed to set up the hardware, and export to the SDK. However running tera term I am met with "connection refused" or "connection timed out". I have managed to accomplish all steps with exception of 12.2 (STDIO) as it is not available in 2018.3. Would there be any suggestions or advice how to remedy this issue? Regards, Luke Abela
  8. Good Day, I am currently working on a project which entails the interfacing of a Nexys 4 DDR to a DAC8803EVM evaluation board. I am however having trouble connecting the generated clock of 50 MHz to the DAC. The DAC requires a clock of 50 MHz for optimal operation. Would it be too much to expect the IOBs of the nexys 4 ddr to output 50 MHz at the board connectors at full signal strength (i.e. minimal to no reflections), or has the board been predesigned with this situation in mind? Kind Regards, Luke
  9. Hello again, Thank you for your assistance, I have now solved my issue. If you could kindly aid with me a final matter however, if you progress further along the tutorial, the tutorial states that you should be able to find a tab known as STDIO, this is unavailable for me on Xilinx SDK 2018.3 Could you kindly provide any information as to have to remedy this? Thank you for your aid, Luke
  10. Hi JColvin, Thanks for the response, I ran through the tutorial and my issue is that block automation is not appearing when I input the Memory Interface Generator, hence why I clicked on it. Would you have any advice on this matter, alternatively is it essential to the setup of the echo server? Regards, Luke Abela
  11. Good day, I am currently attempting to set up an ethernet configuration on the Nexys 4 DDR FPGA and was doing so by following this link: However, my issue arose with the Memory Interface Generator IP. The version of Vivado used for this tutorial was a 2015 edition, my edition is 2018.2. Since the 2015 edition, the run block automation option for the Memory interface generator IP is no longer available, and the page displayed below loads. I viewed the Xilinx tutorial on this generator, however, I have not been able to achieve the same pinouts as are displayed in the tutorial I was following. Could someone kindly advise a course of action? Thank for your time, Regards, Luke Abela