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  1. Thanks for the video. Short version: When I access the DDR through the processor it is not sync with the hardware and is limited to the program speed of the processor. In other word, if I have a bunch of sampled data that are generated by the FPGA (programmable logic) and I want to store all of them in DDR, I need to write a sample at each clock cycle, but processor can not do that. Is there a way to access the DDR directly through the hardware? Long version: As a test design, I created a 16-bit counter and added that as a module to my IP design and connected it to the processor through a GPIO. Thus, the output of the counter is accessible by the processor. I used Xil_Out16(XPAR_PS7_DDR_0_S_AXI_BASEADDR+n*2,sigOut); and sigOut = Xil_In16(XPAR_PS7_DDR_0_S_AXI_BASEADDR+n*2) (n is the index of a for loop that goes for 100 iterations) to first write 100 consecutive readout of the counter to the DDR and then read it and looked at it on the terminal. It seems that every 44 counts are picked up by the processor probably because processor runs the code slower or it takes 44 cycles to go over the for loop and thus I miss the intermediate counter values. To capture all the samples generated by the hardware I need to access the DDR directly through the FPGA hardware. How can I do this? To first
  2. Thank you for the response. It answered most of my questions. So I should be able to write codes in SDK to access the DDR3 memory through the processor. What is the library that I should use and is there an example of the basic functions for read and write into the memory?
  3. On Cora Z7 board, there is an IC that is named "DDR3L memory". How can I use this memory block to write and read data? How can I instantiate it in Vivado? What is the size of the memory? What is the read/write speed? Is there any other way to have a relatively large memory block (100 MBytes for example ) with with at least 5 MHz write speed? My question is sort of general now. So any other board that could do the job, or if you know how to get a 10 MBytes instead of 100, or any other relevant info. will help. Also, if there is an example code or project that you could refer me to would be great. There is also a "Block memory generator" IP in Vivado. Is this related to the external memory on the board or it's for making a memory out of internal memory cells of the FPGA?
  4. The Zynq FPGA that I am looking at for an application has a processor unit and a programmable logic unit. I know how you can write a HDL code to use the logic part. For the processor part it seems that I need to use the IP integrator to get the CPU, peripherals, and interface properly configured and then generate the HDL code for it. In the generated HDL code, "HDL wrapper", the blocks are defined as modules. Then I need to use SDK to program the bit stream and program a C code for the processor (for example). My question is, if I want to have a logic (let's say an 8 bit counter) on the logic part, and then the processor and the XADC that is controlled by the processor, how can I access the output of the 8-bit counter via processors and transfer it to the PC through the USB UART port? Do I need to define another top level HDL file and instantiate the HDL wrapper plus my 8-bit counter code? My question is sort of general for now, so any example or comment would be helpful.
  5. @jpeyron: I tried to run the example you referred me to. But there is no .xpr file on it. How can I open it in Vivado?
  6. I am considering the AXI USB 2.0 Device Controller https://www.xilinx.com/products/intellectual-property/axi_usb2_device.html I need about 400 Mbps total speed. I think the speed on USB UART is around 12 Mbps. Thank you for the link. I might use USB UART for the first round with smaller number of data channels (not the total 128 output channels of my setup). Is there any other way to reach this speed? I need to record a couple of seconds of data. Can I write on a memory with this speed and then transfer it to the computer with a lower speed of USB UART? Is there an example for using the on board RAM?
  7. The total data rate will be less than the full speed of USB 2.0. I can multiplex the lines before feeding the FPGA or pick another board with more IOs. The main question here is 1- Do I need a license? 2- Is there an example of doing it? (without Linux just through the hardware and possibly a C code)
  8. I edited the question and included more details.
  9. Short story: I want to use the Cora board to combined multiple low data rate signals and send it through the USB 2.0 port to a computer. I need the full speed of the USB 2.0. Do I need to buy a license for USB 2.0 from Xilinx to use Vivado for programming it? Is there any example code for running the USB 2.0 you could refer me to? Long story: I have a test setup for a chip that has 128 digitized data outputs less than 4Mbps each. I need to transfer these data outputs into a computer with real-time speed. I thought the easiest way is to use an FPGA, combine the 128 data lines, and send them through the USB port. I am looking at the Digilent Cora Z7 board that has the USB 2.0 port on the board. When I was reading Xilinx USB 2.0 manual I noticed the licensing part. Does the license come with the Digilent boards? Do I need to purchase a license to activate the USB IP on Vivado and programming the FPGA? Also, it seems that it is a lot of work to figure out the USB IP and getting it working. Is there any example code for running the USB 2.0 you could refer me to? Would it be easier if I use Ethernet or something else?