osti

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  1. The frequency fine tuning actually worked quite nicely. Thanks again! I measured the temporal drift with respect to a Stanford Signal Generator (SG384). In the 1 to 100 kHz range, the relative mismatch of the clocks was about 1e-6 (i.e. 1 kHz on the DD was about 0.99988 kHz on the SG). In the MHz regime (actually, 5.204 MHz), we could then see phase instabilities with transient drifts of about one 192 ns cycle over a few seconds to minutes. For the actual experiment, this was of no importance, since the setup was re-triggered at 1 kHz. We could see, however, that the "wait time" between the trigger of the logic analyzer and the pattern generator introduces a relative jitter of about 1e-3. To circumvent, we installed an external Delay Generator (DG584) to "jump" over 200 µs, and used the DD to generate the desired pulse patterns (to then gate a detector). We will certainly make much more use of this device in the future
  2. Hi @attila, Wow! That is really great, thanks a lot. We will directly use this on Tuesday and I will thank you with some photos and figures Best, osti
  3. Thank you very much, @attila; I guess for the first experiment we can keep it simple and neglect temporal jitter/drift during time scales < 10 µs.
  4. Thanks! I wasn't sure where best to put it.
  5. Hi, we are evaluating to use a bunch of Digital Discovery boards for experimental physics; more specifically: to synchronise / control certain motors / detectors / other equipment. (1) Is it possible to synchronise the Discovery to some external reference clock (10 MHz is quite common), in order to reduce temporal jitter? (2) In another use case, we would like to control an experiment running at 5.204 MHz; it would be great if the system clock (100 MHz) could somehow be tweaked towards 98.87 MHz; even at the risk of warranty void. Any ideas? Could we carefully detune or even replace a crystal? Thanks for your time – osti