chaitusvk

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    chaitusvk reacted to [email protected] in Amplitude modulation with DDS generator   
    @chaitusvk,
    I notice that the on and off periods are ... not on an obvious integer spacing.  Is there some greatest common sublength that all of the bits are described with?  Is the carrier a multiple of this subwidth?
    Your goal is to create this signal, right?  I think my goal would follow @xc6lx45's approach: create some form of NCO for the carrier, and then use multiples of it (if possible) for handling bit periods.  You might find this article, or even this one, valuable back-reading on the topic.
    Dan
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    chaitusvk reacted to [email protected] in Amplitude modulation with DDS generator   
    The carrier phase alignment question is pretty important.
    What carrier frequency is this thing supposed to be operating at?  And ... is it in the range of what an FPGA can create?
    Dan
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    chaitusvk reacted to xc6lx45 in Amplitude modulation with DDS generator   
    You could use the multiplication operator "*" in Verilog (similar VHDL).
    For example, scale the "mark" sections (level 10) by 1024, the "space" sections (level 3) by 307. This will increase the bit width from 12 to 22 bits, therefore discard the lowest 10 bits and you are back at 12 bits. Pay attention to "signed" signals at input and output, otherwise the result will be garbled.