chaitusvk

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Everything posted by chaitusvk

  1. Hi I made a custom axi counter which interupts processor for every 1 sec , i read counter value through axi bus , i have written driver for reading BASE_reg of axi peripheral which is working fine. when i activate interrupt by including the deatils of peripheral in system when i activate interrupt through system-user.dtsi iam not able to read the device .... my acces to axi_peripheral register is blocked please help me how to access the axi_register while enabling the interrupt system-user.dtsi simmod.c
  2. Rather than using the BSP's you have to create your own hard ware ... use petalinux-config --get-hw-description=<PATH TO design_1_wrapper_hw_platform_0> I wish the following videos sloves your problem
  3. My system is as shown in the diagram (ZYBO Z7-20), i am able to run bare metal interrupt program .i have seen peta linux UIO interrupt but i have to generated interrupt at 1ms rate On interrupt i have to read axi slave reg and send that in UDP packet i choose interrupt because to reduce burden on processor is there is any way to solve this issue please help me
  4. @elodg I tried running demo after compiling in VIVADO 2019.1 , but it shows HDMI unplugged, but my PC is detecting the port please confirm me that first i have to choose 1. Display resolution and then 2. I have to start streaming with option "5"
  5. I am newbie with ZYBO Z7-20 working on hdmi in demo , i have done as shown on github digilent project page in VIVADO 2019.1 , But unable to get the video output ,but my system detecting the Board as DGL 720P CEA and UART port shows HDMI UNPLUGGED i have tried hdmi pass through , My system is not detecting the display itself i see video capture .state is video disconned in VIdeoinitilaztion it not changed any where ..and video_start function wont work Please Help ... Whether i have to change vivado version or any code
  6. Hi I am working on HDMI pass through example from Digilent work shop manual i connected as shown in manual but getting error showimg [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_axi4s_vid_out_0/video_in(100000000) and /v_vid_in_axi4s_0/video_out(200000000) can any one please help in in solving the issue clk out_1 is set to 200Mhz after going through the Xlinx Forum if AXi is made external then its frequency goes to 100Mhz, But how to change i dont know ...
  7. Thank you very elodg ....
  8. I can use linux .... and i want to use HLS
  9. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  10. I have implemented a small system with ZYBO-Z7 20 , It will send the switch status through Ethernet interface . Implemented with AXI GPIO and LWIP ,UNICAST ,BOARD HAS CONSTANT IP and REMOTE IP is CONSTANT. i am not using DNS I am able to Send packets if Board is connected directly to LAPTOP and i am able to PING the Board from LAPTOP But when the Same setup when connected to Switch [allied telesis] i am not able ping the board and no packets are flowing ... Can any one help me where i have to look...
  11. @[email protected] Thank you very much Dan it is issue with linux system ...i am using UBUNTU 16.04 and installed drivers by executing install drivers in data directory i tried the same example in Windows 7 but vivado 2016.1 it is working fine I have POST the bug in XLINX FORUM
  12. @[email protected] Thank you for sending time dan i am getting what i am writing , two xil_prints i added first one giving me what i am writing second one giving blank i have create different ip like leds are given to lsb of reg_slv not nothing working ...
  13. I am always getting "0" what ever the input put there some mistake i am making ....i think so
  14. @[email protected] just i am creating 8 bit adder i will write A to one axi_slv_reg and B to other reg sum should be in third slv_reg i am unable to create correct functinality... thank you @[email protected]
  15. @jpeyron after checking file groups i am not getting synthesis error but i am not able to make SUM correctly sum is always zero even i create axi peripheral with just led out from slv_reg0 ...i am unable to make it work... i have attached the files ..it is created in VIvado 2019.1 please help me ... at down i have attached ip core please check total source at https://github.com/chaitusvk/axi_peripheral thank you very much @jpeyron
  16. i am a new bee creating simple axi adder with help of the video but i am getting module adder not able to found can any one help me
  17. @[email protected] i have another question How to generate 1khz square which is synchronous to 1pps ie both posedges has to be at same time 1pps: from GPS reciver i have 10mhz from Rb Atomic clock I tried Resetting decade counters with 1pps to achieve sync but it around 200 ns i need even less around 50 ns please help me i am designing IRIG-B code from GPS module with FPGA
  18. thank you @[email protected] what i am creating is IRIG-B am signal ,it has three digital symbols " MARK " , " 1 " , " 0 " MARK or Reference is defined by square pulse : 8msec high 2 msec low 80% duty cycle 1 is defined by : 5msec high 5 msec low 0 is defined by : 2 msec high 8 msec low Every symbol start with HIGH state
  19. @[email protected] Can you please help how to do carrier phase alignment ..please clock driving DDS and producing PWN is same in my design
  20. 1 khz is carrier frequency .... i will be using zyboz7 board and each symbol takes 10 ms