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Everything posted by chaitusvk

  1. HI , i want to use GPS Pmod for time reading In indoor , i have GPS external antenna Does Pmod have SMA connector built ? or any suggestion to connection external active antenna
  2. Able to generate with help of hysc , vsync and pixel clock
  3. I am working with Zybo Z7 board i wan to generate interlaced video does it support it
  4. Hi, i am newbie in video processing on fpga , started with Zybo z7 demo ..afte going through this blog post Adam Taylor video tutorials i made it working At present my project is to generate text overaly like this Adam Taylor Text overlay i have this tutorial Zybo test pattren generator Just small design with 1.Test pattren generator 2. VTC 3. Axi to RGB 4. RGB to DVI clk speed i choose 148.5Mhz dedrived from 100mhz of processor With this design i ended up in Timing Not met error .... my Questions are 1. Do you use any xdc const
  5. Thank you very much @[email protected] you are a great mentor ... i have solved it is issue of async counter module decade_counter( input clk, input reset, input load, input[3:0] data, output [3:0] hours_u_count ); reg[3:0] count; [email protected](negedge clk or posedge load or posedge reset) begin if(reset) count <= 4'b0000; else begin if(load) begin count <= data ; end else begin if(count == 4'b1001) count <= 4'b0000; else count <= count +1; end end
  6. Thank you @[email protected] .. Sorry for my poor description i figured it out today .. . i am connecting one of pins(Mark) of my IP to interrupt of processor if i remove this evering is working fine ..for 1hour ... i think this is beacuse of Infering latches ..please confirm me .. if i connect it my ip to interrupt pin of processor it will be power down my ip with in 5 minutes ... Thank you .....
  7. Hi @[email protected], I am decoding IRIG signal ,some times all my outputs dissapper , 1. when i remove unused register it was working fine . in my fsm there are states where reaching is not trivial only are 1hour i can reach the state ... 2. when i dont connect all output signals in xdc file also leads to disaapring of signals 3. is there any racing condition ... please help me ...
  8. I am folowing this Interrupt Tutorial I am not able to find arch/Kconfig file in petalnux project files ...please suggest me where i have to look how to enable
  9. Thanks @lonel i migrated to uio drivers from custom they now working Thanks for the support ...
  10. Thank @lonel 1. I did not understand compatble string ...i am newbie 2. i have not opened the device in wite mode opened in only read mode. 3. hellosim just opens and reads the device. 4. In simmod read ie. Kernel driver i am reading membase address .. my main probelm is if i dont include the device in Device tree i am able to read the Device perfectly . but i need to read Device on interrupt so i added it to Device tree . When i add it to Device Tree Device, Base mem Address is becmming NULL i dont know i to add Device to Device
  11. Hi I made a custom axi counter which interupts processor for every 1 sec , i read counter value through axi bus , i have written driver for reading BASE_reg of axi peripheral which is working fine. when i activate interrupt by including the deatils of peripheral in system when i activate interrupt through system-user.dtsi iam not able to read the device .... my acces to axi_peripheral register is blocked please help me how to access the axi_register while enabling the interrupt system-user.dtsi simmod.c
  12. Rather than using the BSP's you have to create your own hard ware ... use petalinux-config --get-hw-description=<PATH TO design_1_wrapper_hw_platform_0> I wish the following videos sloves your problem
  13. My system is as shown in the diagram (ZYBO Z7-20), i am able to run bare metal interrupt program .i have seen peta linux UIO interrupt but i have to generated interrupt at 1ms rate On interrupt i have to read axi slave reg and send that in UDP packet i choose interrupt because to reduce burden on processor is there is any way to solve this issue please help me
  14. @elodg I tried running demo after compiling in VIVADO 2019.1 , but it shows HDMI unplugged, but my PC is detecting the port please confirm me that first i have to choose 1. Display resolution and then 2. I have to start streaming with option "5"
  15. I am newbie with ZYBO Z7-20 working on hdmi in demo , i have done as shown on github digilent project page in VIVADO 2019.1 , But unable to get the video output ,but my system detecting the Board as DGL 720P CEA and UART port shows HDMI UNPLUGGED i have tried hdmi pass through , My system is not detecting the display itself i see video capture .state is video disconned in VIdeoinitilaztion it not changed any where ..and video_start function wont work Please Help ... Whether i have to change vivado version or any code
  16. Hi I am working on HDMI pass through example from Digilent work shop manual i connected as shown in manual but getting error showimg [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_axi4s_vid_out_0/video_in(100000000) and /v_vid_in_axi4s_0/video_out(200000000) can any one please help in in solving the issue clk out_1 is set to 200Mhz after going through the Xlinx Forum if AXi is made external then its frequency goes to 100Mhz, But how to change i dont know ...
  17. I can use linux .... and i want to use HLS
  18. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  19. I have implemented a small system with ZYBO-Z7 20 , It will send the switch status through Ethernet interface . Implemented with AXI GPIO and LWIP ,UNICAST ,BOARD HAS CONSTANT IP and REMOTE IP is CONSTANT. i am not using DNS I am able to Send packets if Board is connected directly to LAPTOP and i am able to PING the Board from LAPTOP But when the Same setup when connected to Switch [allied telesis] i am not able ping the board and no packets are flowing ... Can any one help me where i have to look...