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  1. Hi I am working on HDMI pass through example from Digilent work shop manual i connected as shown in manual but getting error showimg [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_axi4s_vid_out_0/video_in(100000000) and /v_vid_in_axi4s_0/video_out(200000000) can any one please help in in solving the issue clk out_1 is set to 200Mhz after going through the Xlinx Forum if AXi is made external then its frequency goes to 100Mhz, But how to change i dont know ...
  2. Thank you very elodg ....
  3. I can use linux .... and i want to use HLS
  4. I have time stamp on video in real time as shown in fig ,I have Zybo Z7 FPGA board can any one please help me how to text overlay and how the overlaying text can be changed dynamically please guide me .. Thanks in advance ....
  5. I have implemented a small system with ZYBO-Z7 20 , It will send the switch status through Ethernet interface . Implemented with AXI GPIO and LWIP ,UNICAST ,BOARD HAS CONSTANT IP and REMOTE IP is CONSTANT. i am not using DNS I am able to Send packets if Board is connected directly to LAPTOP and i am able to PING the Board from LAPTOP But when the Same setup when connected to Switch [allied telesis] i am not able ping the board and no packets are flowing ... Can any one help me where i have to look...
  6. @D@n Thank you very much Dan it is issue with linux system ...i am using UBUNTU 16.04 and installed drivers by executing install drivers in data directory i tried the same example in Windows 7 but vivado 2016.1 it is working fine I have POST the bug in XLINX FORUM
  7. @D@n Thank you for sending time dan i am getting what i am writing , two xil_prints i added first one giving me what i am writing second one giving blank i have create different ip like leds are given to lsb of reg_slv not nothing working ...
  8. I am always getting "0" what ever the input put there some mistake i am making ....i think so
  9. @D@n just i am creating 8 bit adder i will write A to one axi_slv_reg and B to other reg sum should be in third slv_reg i am unable to create correct functinality... thank you @D@n
  10. @jpeyron after checking file groups i am not getting synthesis error but i am not able to make SUM correctly sum is always zero even i create axi peripheral with just led out from slv_reg0 ...i am unable to make it work... i have attached the files is created in VIvado 2019.1 please help me ... at down i have attached ip core please check total source at thank you very much @jpeyron
  11. i am a new bee creating simple axi adder with help of the video but i am getting module adder not able to found can any one help me
  12. @D@n i have another question How to generate 1khz square which is synchronous to 1pps ie both posedges has to be at same time 1pps: from GPS reciver i have 10mhz from Rb Atomic clock I tried Resetting decade counters with 1pps to achieve sync but it around 200 ns i need even less around 50 ns please help me i am designing IRIG-B code from GPS module with FPGA