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  1. Hi, I have a Arty Z7 board. I am using petalinux 2017. What I understand is that I have xdevcfg to load bitstream after linux has been loaded. I tried loading the test.bit using cat test.bit > /dev/xdevcfg and it works perfectly. Now I want to load an encrypted bitstream, with keys in the bbram. I cannot figure out how. What I understand is that I will need an encrypted bitfile first, but the tools given by xilinx creates an encrypted .bin file not a .bit file, so firstly I am not sure how do I create that. Second, I feel I will have to turn something on to let the device know that it should now pass the bit file through the AES engine. AES engine is turned on, that I have checked. Regards, Hasan
  2. Hello, I am using a ARTY Z7 digilent board with xc7020 zynq core. I am trying to program AES keys into the BBRAM. I am following the Secure Boot of Zynq-7000 SoC application document provided by Xilinx. It is using the secure key driver provided by Xilinx. It is not working. What I understand from it is that there has to be a physical printed connected coming out from MIO pins to the JTAG pins. I checked the ARTY Z7 schematic, and I couldn't find the pin connection. I may have missed something. Can you tell me how can I program AES keys into the BBRAM ? Regards, Hasan
  3. Hi, I have an issue which I really cannot understand. I have a traffic generator connected to a AXI Stream Data FIFO which is connected to a AXI DMA. AXI DMA is connected via the interconnect to the HP port. I am reading the data in the Data FIFO by connected its data_read line to my custom IP which just reads the data. The problem is that the amount of data transferred is not correct with every transaction. The traf_gen sends data in 16 data bursts, and whatever length I give in simple_dma_transfer() function, the data copied is always 16. I am not sure why is that.
  4. Is there then any way I can do what I wish to do ? Maybe pass a variable from the top module to the sub module ?
  5. Hi, So I created a custom IP which just reads the data_read from the FIFO buffer. I would like to generate an interrupt when the FIFO buffer exceeds a certain amount. I have enabled the interrupt when making my custom IP. There is an example in the INTR.v file which generates an interrupt after a certain time. I would like to generate an interrupt as soon as the data_read exceeds. I understand I will have to set the intr register. How do I use the intr register from the top module ? This is what I have done, its obviously wrong. // Users to add ports here input wire clk, input wire [31:0]ReadData, // User ports ends // Do not modify the ports beyond this line ,... ... ... // Instantiation of Axi Bus Interface S_AXI_INTR myip_v1_0_S_AXI_INTR # ( .C_S_AXI_DATA_WIDTH(C_S_AXI_INTR_DATA_WIDTH), ... .S_AXI_RREADY(s_axi_intr_rready), .intr(), .irq(irq) ); // Add user logic here always @ ( posedge clk ) begin if ( s_axi_intr_aresetn == 1'b0) begin assign myip_v1_0_S_AXI_INTR_inst.intr = {C_NUM_OF_INTR{1'b0}}; end else begin if (ReadData >= 1024) begin assign myip_v1_0_S_AXI_INTR_inst.intr = {C_NUM_OF_INTR{1'b1}}; end else begin assign myip_v1_0_S_AXI_INTR_inst.intr = {C_NUM_OF_INTR{1'b0}}; end end end // User logic ends
  6. HasanWAVE

    Custom IP interrupt

    Hello, I am trying to make a custom IP with an interrupt. I selected the interrupt option when creating my IP block. The problem that I am having is that, there are 5 slave registers in the custom_ip_intr.v file (intr_en, global_intr_en, ack, status, intr_pending), and from what I understand is that I would have to control them via the ARM to enable, set, reset and disable them. I have added those registers in the user ports and also in the top module, but I cannot get the registers memory mapped addresses in the SDK which I can control. How could I do that ? Regards, Hasan
  7. Hi @jpeyron Like in this example https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_intr_example.c?_ga=2.11499126.33107880.1566472821-1015055952.1563367754 they are using input pin = 14 which I believe would be the pin connected to the swtich. How can I determine which mine would be connected to which MIO ? Regards, Hasan helloworld.c
  8. Hi @jpeyron I am still a bit unsure regarding using Vivado, so just to make sure my understanding is correct. If I want to use the GPIO on the PS (lets say IO35), how will I know which MIO pin is this connected to ? Also, the IOMODULE made will be using the IO hardware which is already on the Zynq or will this make an IP block on the fabric ? Regards, Hasan
  9. Hello, I have an ARTY Z7 board and I am trying to use the push buttons as an interrupt source for the PS. I want to use GpioPS not the FPGA Gpio. What I cannot understand is which pin will my switch buttons be located on ? Which pin should I put in XGpioPs_SetDirection(Gpio,XX,0x0) in the XX field. I read the schematic but couldn't understand. What I understand is that XX value would be one of the MIO values which use the GPIO, but I can't seem to make it work. Regards, Hasan
  10. Hi Jon, Thank you. It has worked. The problem what I was doing was I was using the AXI Interrupt controller block in Vivado and using the SCUGIC driver in the software. My question right now is, if I have more than 16 interrupts then I will have to use the AXI Interrupt Controller. What is the driver API which I would have to use for that ? https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers I am following the above link examples in a lot of my development. Regards, Hasan
  11. Hi, I have a ARTY Z7 digilent board with ZYNQ 7020 chip. I am trying to have a simple interrupt running, that when I turn on the SW0, it causes an interrupt and prints "HelloWorld". I have followed the examples given in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/examples/xscugic_example.c and https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/gpio/examples/xgpio_intr_tapp_example.c. But I am not sure where I am missing something. This is my design board diagram I have made on Vivado. Could anyone help me where I might be doing wrong. Is my diagram of Vivado correct ? Regards, Hasan