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  1. I am getting this warning [Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.
  2. Hi @jpeyron I followed the procedure as you mentioned in the link https://miscircuitos.com/sinus-wave-generation-with-verilog-using-vivado-for-a-fpga/?_ga=2.106154691.1163116266.1566581309-2054910748.1538715088. But still it is working only in simulation phase but not in Hardware platform. The top module of my verilog code and XDC files are attatched. 1.txt 2.txt
  3. Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware). send.txt
  4. Hi everyone Whether my question is clear? I need the specific answer for my question.
  5. Hi Is it possible to display the dumped FPGA data with the help of oscilloscope present in Waveforms software. If so what will be the connections means which pins to which pins.
  6. Hi @jpeyron I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. As you mentioned, I have also connected four gnd pins of FPGA to the four gnd pins of analog discovery. After that I opened the Waveforms software, added all the buses DIO 0 to DIO 15 of the logic analyzer but unable to see the dumped waveform of FPGA in the Waveforms software. Help me to solve the problem.
  7. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog dis