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About marsee101

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  1. Hi, I think that it is necessary to connect MDIO of Ethrnet 0 to MIO as written on the circuit diagram. Even with "Ethernet PHY on Zybo board using Vivado 2017.2", it seems that bugs could be fixed by connecting MDIO of Ethrnet 0 to MIO.
  2. Hi, congratulations. Ethrnet 0 MDIO seems to need to connect to MIO.
  3. Hi, Did you create a Vivado 2017.2 project using the ZYBO board file? If so, how about trying to change the setting of MDIO from EMIO to MIO by opening processing_system 7 _ 0 of the block design? For details, refer to the following URL.
  4. MDIO has been assigned to MIO by adding the following line to "Xilinx \ Vivado \ 2017.2 \ data \ boards \ board_files \ zybo-z 7-20 \ A.0 \ preset.xml". <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" />
  5. The project of Vivado 2017.2 used is a project of AXI GPIO created using Zybo Z7-20 board file.
  6. Ubuntu 14.04 worked on ZYBO Z7-20, but at first Ethernet did not work. The cause was that MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 was connected to EMIO. In the circuit diagram of ZYBO Z7, MDIO is connected to MIO52, MIO53. In the board file, should I connect MDIO of Ethrnet 0 of PS Peripheral I / O Pins to MIO? Currently, since we connected MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 to MIO, Ubuntu 14.04's Ethernet now works on ZYBO
  7. We use Digilent Inc. ZYBO board.,400,1198&Prod=ZYBO Please go to the generation of the bit stream First "the HDMI input of ZYBO (public project) 9 to be output to the VGA output" by reference to Vivdo 2015.2 by preparing the dvi2vga_lap project. The 1280x720 60P image of input from the HDMI input of ZYBO in real time and then output to the V
  8. Hi My name is Masaaki Ono. I am writing a blog that FPGA of the room in Japanese. I have installed Ubuntu 14.04 LTS and OpenCV to ZYBO.