marsee101

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marsee101 last won the day on October 9

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About marsee101

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  1. Hi, I think that it is necessary to connect MDIO of Ethrnet 0 to MIO as written on the circuit diagram. Even with "Ethernet PHY on Zybo board using Vivado 2017.2", it seems that bugs could be fixed by connecting MDIO of Ethrnet 0 to MIO.
  2. Hi, congratulations. Ethrnet 0 MDIO seems to need to connect to MIO.
  3. Hi, Did you create a Vivado 2017.2 project using the ZYBO board file? If so, how about trying to change the setting of MDIO from EMIO to MIO by opening processing_system 7 _ 0 of the block design? For details, refer to the following URL.
  4. MDIO has been assigned to MIO by adding the following line to "Xilinx \ Vivado \ 2017.2 \ data \ boards \ board_files \ zybo-z 7-20 \ A.0 \ preset.xml". <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" />
  5. The project of Vivado 2017.2 used is a project of AXI GPIO created using Zybo Z7-20 board file.
  6. Ubuntu 14.04 worked on ZYBO Z7-20, but at first Ethernet did not work. The cause was that MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 was connected to EMIO. In the circuit diagram of ZYBO Z7, MDIO is connected to MIO52, MIO53. In the board file, should I connect MDIO of Ethrnet 0 of PS Peripheral I / O Pins to MIO? https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf Currently, since we connected MDIO of Ethrnet 0 of Peripheral I / O Pins of PS of ZYBO Z7 to MIO, Ubuntu 14.04's Ethernet now works on ZYBO Z7-20. This situation was also the same for ZYBO. In previous ZYBO_zynq_def.xml, MIDO was connected to MIO.
  7. We use Digilent Inc. ZYBO board. http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO Please go to the generation of the bit stream First "the HDMI input of ZYBO (public project) 9 to be output to the VGA output" by reference to Vivdo 2015.2 by preparing the dvi2vga_lap project. https://translate.google.co.jp/translate?sl=ja&tl=en&js=y&prev=_t&hl=ja&ie=UTF-8&u=http%3A%2F%2Fmarsee101.blog19.fc2.com%2Fblog-entry-3255.html&edit-text=&act=url The 1280x720 60P image of input from the HDMI input of ZYBO in real time and then output to the VGA terminal by Laplacian filter processing.This is a project of Vivado 2015.2. It shows the procedure. · Connected to the HDMI terminal of ZYBO from laptop HDMI terminal. · It was connected to a display from VGA terminal of ZYBO. · Put the power of ZYBO. · Configure the bit stream to ZYBO in Vivado. Disk top screen of the notebook computer will be displayed on the screen that is connected to the ZYBO. When the SW0 of ZYBO to 1, Laplacian filter processing is performed. For an example see this URL. https://translate.google.co.jp/translate?sl=ja&tl=en&js=y&prev=_t&hl=ja&ie=UTF-8&u=http%3A%2F%2Fmarsee101.blog19.fc2.com%2Fblog-entry-3248.html&edit-text=&act=url Download URL https://github.com/marsee101/dvi2vga_lap
  8. Welcome!

    Hi My name is Masaaki Ono. I am writing a blog that FPGA of the room in Japanese. I have installed Ubuntu 14.04 LTS and OpenCV to ZYBO. https://translate.google.co.jp/translate?sl=ja&tl=en&js=y&prev=_t&hl=ja&ie=UTF-8&u=http%3A%2F%2Fmarsee101.blog19.fc2.com%2F&edit-text=