• Content Count

  • Joined

  • Last visited

About chainastole

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. There is a great tutorial from a collective of authors of University of Strathclyde on FPGA, which among all other interesting staff has a part on custom IP creation with accompanying lab. See and
  2. Not sure what does it mean VHDL code for PMOD ALS. If you mean the code of the IP to communicate with it, then I can answer regarding Vivado IDE. Digilent provides the IPs library, which PMOD ALS is a part of. When you add this library as an additional repository and PMOD ALS as an IP of your design, you have all the access to it, including Verilog (not sure about VHDL) of the IP interface and the C code of the driver. The comprehensive instructions are at
  3. Hi, @JColvin The lab I am talking about is It is not a Digilent tutorial. It is written by a collective of authors from University of Strathclyde. It was very convenient for me as a newbie in FPGA. @hbucher at states that "... in Vivado HLS you don't need the board file because it only uses the device part". If it is really so, I'll definitely go this direction. The only thing is I don't understand why " .. you don't need the board file ...". All the projects from aforementioned tutorial I'd completed until now according to RTL entry flow and involving board buttons and LEDs do needed the board awareness expressed in board constraint or board master files. Will be glad to receive an explanation. As for my second question I do detected now that my Arty Z7-20 part number is xc7z020clg400-1. It can be seen in "Project Summary" in one of my previously performed labs.
  4. I am trying to complete the Vivado HLS lab written for Digilent ZedBoard, while possessing Digilent Arty-Z7020 and working with Vivado 2019.1 WebPack. As is the problem described by original author I don’t see the board in Vivado HLS “Device Selection Dialog”. I understood, there are no pre-built board files for Vivado HLS for Arty (BTW this is solved for ZedBoard). I understood, two methods are proposed for device entry: a) add the board file manually into Vivadohls_board.xml b) not bother with board but rather add the device as part. I have obstacles in implementing both of them and they are: 1. I can’t find Vivadohls_board.xml file nowhere under <myInstallation>/Xilinx. 2. The Arty-Z7020 Part is XC7Z020-1CLG400C, while the Vivado HLS device selector has xc7z020clg400-{1,2,3} and xc7z020iclg400-1L. I don’t know what is the match. May be it is not significant. The thread is duplicated in corresponding thread at
  5. It appears there are 2 types of USB cables - with data and power only. The simplest method to determine the type is to connect mobile to computer. If seen, it is data cable. Appeared my USB cable was of power only type. Luckily I had a data type in my home stock too and after connection the problem resolved. Lucky for me because my ToDo list included: 1) Wait for replies on forums; 2) Re-install Vivado; 3) Try on my work environment; 4) Use mini-SD instead; 5) Try to power with separate power cable; 6) Try another computer after installing Vivado on it;
  6. Hi, @JColvin. So far I experience some difficulties ( ), related to opening hardware target and tend to blame the USB cable, can you please elaborate on what is the USB cable intended for power only. I use USB A to micro B? Isn't it sufficient information to determine the cable's type?
  7. Hi, Vivadong69. Were you be able to resolve? Did USB cable change help?
  8. This request for help is duplicated at Xilinx forum. I started working with Xilinx Arty Z7-20 development board with Vivado 2019.1. I fail to open hardware target. The localhost is seen to be connected but Hardware Manager is said to be unconnected and after refreshing server I get the following: refresh_hw_server {localhost:3121} WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121] Check to make sure the cable targets connected to this machine are properly connected and powered up, then use the refresh_hw_server command to re-register the hardware targets. 1. I tried both “QSPI” and “JTAG” settings of JP4 jumper. In wain. 2. I learned from Xilinx and Digilent forums the possible culprit is poor cables drivers installation. I remember I included the cables drivers during initial installation. 3. I re-ran Vivado update without uninstall and included cable drivers again (checked their respective checkbox). But after second trial I saw they are again proposed to be installed – their checkbox is still unchecked. The hardware target wasn’t opened. 4. I followed the instructions in I ran the cables driver installation batch file as administrator in Windows and it seemed to success. Log is attached. But in wain. The hardware target wasn’t opened. 5. Need to emphasize the cable I use to power up the board and to program it is the plainly usual USB A to micro B, wihch I connect to USB port of the board. From reading the Vivado programing and debugging ug908 document it could built up an impression that special supported JTAG cables are needed. But it would be too strange - the Arty Z7 board manual doesn't mention any need in a special cable and Digilent specifies this cable functionality is already built in into their boards. Please, help. install_drivers_wrapper.log