saif91

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  1. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY lpm; USE lpm.lpm_components.all; ---------------------------------------------------------- ENTITY vga IS GENERIC ( Ha: INTEGER := 96; --Hpulse Hb: INTEGER := 144; --Hpulse+HBP Hc: INTEGER := 784; --Hpulse+HBP+Hactive Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP Va: INTEGER := 2; --Vpulse Vb: INTEGER := 35; --Vpulse+VBP Vc: INTEGER := 515; --Vpulse+VBP+Vactive vbp Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP PORT ( clk: IN STD_LOGIC; --50MHz in our board red_switch, green_switch, blue_switch: IN STD_LOGIC; pixel_clk: BUFFER STD_LOGIC; Hsync, Vsync: BUFFER STD_LOGIC; R, G, B: OUT STD_LOGIC_VECTOR(9 DOWNTO 0); nblanck, nsync : OUT STD_LOGIC); END vga; ---------------------------------------------------------- ARCHITECTURE vga OF vga IS SIGNAL Hactive, Vactive, dena: STD_LOGIC; SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL hPos: integer; SIGNAL vPos : integer; SIGNAL videoOn : STD_logic; constant picture_size : Integer:=9000; -------------------------------------------------------------- begin ------------------------------------------------------- --Part 1: CONTROL GENERATOR ------------------------------------------------------- -- --Static signals for DACs: nblanck <= '1'; --no direct blanking nsync <= '0'; --no sync on green --Create pixel clock (50MHz->25MHz): PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN pixel_clk <= NOT pixel_clk; END IF; END PROCESS; --Horizontal signals generation: PROCESS (pixel_clk) VARIABLE Hcount: INTEGER RANGE 0 TO Hd; BEGIN IF (pixel_clk'EVENT AND pixel_clk='1') THEN Hcount := Hcount + 1; IF (Hcount=Ha) THEN Hsync <= '1'; ELSIF (Hcount=Hb) THEN Hactive <= '1'; ELSIF (Hcount=Hc) THEN Hactive <= '0'; ELSIF (Hcount=Hd) THEN Hsync <= '0'; Hcount := 0; END IF; END IF; END PROCESS; --Vertical signals generation: PROCESS (Hsync) VARIABLE Vcount: INTEGER RANGE 0 TO Vd; BEGIN IF (Hsync'EVENT AND Hsync='0') THEN Vcount := Vcount + 1; IF (Vcount=Va) THEN Vsync <= '1'; ELSIF (Vcount=Vb) THEN Vactive <= '1'; ELSIF (Vcount=Vc) THEN Vactive <= '0'; ELSIF (Vcount=Vd) THEN Vsync <= '0'; Vcount := 0; END IF; END IF; END PROCESS; -- ---Display enable generation: dena <= Hactive AND Vactive; ------------------------------------------------------- --ROM instantiation: myrom: lpm_rom GENERIC MAP ( lpm_widthad => 9, --address width lpm_outdata => "UNREGISTERED", lpm_address_control => "REGISTERED", lpm_file => "2colom", --data file lpm_width => 10) --data width PORT MAP ( inclock=>NOT pixel_clk, address=>address, q=>intensity); --Create address (row number): PROCESS (Vsync, Hsync) VARIABLE line_counter: INTEGER RANGE 0 TO Vd; VARIABLE line_counter2: INTEGER RANGE 0 TO Hc; BEGIN -- IF (Vsync='0') THEN -- line_counter := 0; -- ELSIF (Hsync'EVENT AND Hsync='1') THEN -- IF (Vactive='1') THEN -- line_counter := line_counter + 1; -- END IF; -- END IF; IF (Vsync='0') THEN line_counter := 0; ELSIF (Hsync'EVENT AND Hsync='1') THEN IF (Vactive='1') THEN line_counter := line_counter + 1; END IF; END IF; IF (Hsync='0') THEN line_counter2 := 0; ELSIF (pixel_clk'EVENT AND pixel_clk='1') THEN IF (Hactive='1') THEN line_counter2 := line_counter2 + 1; END IF; END IF; address <=conv_std_logic_vector(line_counter , 9); end process; -------- --Assign color values to R/G/B R<=intensity WHEN red_switch='1' AND dena='1' ELSE (OTHERS=>'0'); G<=intensity WHEN green_switch='1' AND dena='1' ELSE (OTHERS=>'0'); B<=intensity WHEN blue_switch='1' AND dena='1' ELSE (OTHERS=>'0'); ------ END vga; now am doing simple display image i save at rom as .mif to display to VGA and use clock 24 mhz but image not display not clear ?
  2. D@n thanks a lot Take advantage of your comment and your tutorials
  3. hello everyone, i am using DE1-SoC Altera try convert image to .hex or .mif how? i was working project display text at ram stocked formula .hex or .mif then i save it, show through VGA has been done!!! i read this topic how he did his project