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dmeads_10

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Posts posted by dmeads_10

  1. Okay, I was referring to the specific model number. When you look at the ZMOD ADC 1410 there are three different models, each with a different max sample frequency, I am just wondering which one is included when you purchase the board with the ADC option. 

    Thanks for the feedback tho, I am planning to use it for some intermediate level DSP exploration, along with some SDR stuff and making a hobbyist service monitor for my handheld radio. any option of the ADC would be fine for my projects I am just wondering which one is included when you buy it. 

  2. Hello!

    working with microblaze and UART on the ARTY S7-25 board and having IO constraints issues. 

    When I include the master XDC file provided by digilent, Vivado gives me an error (when i open the synthesized design) saying that it cannot place the UART pins because of user constraints. Bitstream can still be generated successfully, i havent actually tried to run the UART because I dont want to screw anything up.

    When I dont include the XDC file, the tools automatically route the UART_tx and UART_rx to pins R12 and V12, respectively, however in the XDC file they are filpped (UART_tx is on V12 and UART_rx is R12), which is causing the error. You can see the attatched picture of the auto-routing assigning UART_rx to V12. 

    image.png.6d66ab334ade4fc3e647084d6ed7f963.png

    Here is the XDC code:

    ## USB-UART Interface
    #set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
    #set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in

    which is the correct way to assign pins?

  3. Hey guys!

    Genesys 2 for sale:

    - New but open box, all accessories included. 

    - Still has unused Vivado voucher for the Kintex part on the board (expires in late october of this year)  

    ebay link: https://www.ebay.com/itm/144134145928

     

    Thanks for looking! ( I am going to post this to the EEVblog too so if you see it there just know its me)

    Message if interested

     

     

     

  4. On 7/18/2021 at 7:45 AM, zygot said:

    Without the proper thermal conductivity analysis, and a bit of knowledge, it's quite possible to make things worse by slapping a "looks like" hunk of metal onto the top of your FPGA and declaring victory.

    @zygot

    Yes good point, perhaps i should explain what I did better. I only used the Blue plastic piece from the heat sink part number above. When the original yellow clip came broken and the entire thing came off,  I unscrewed the fan, and cleaned the old thermal pad off from the original passive aluminum piece. When the new one arrived, I only used the clip from it (because I couldn't find the separate clip part, only heatsink+clip together), however used the original passive heatsink itself, and screwed the fan back on. 

     

    On 7/23/2021 at 10:39 AM, zygot said:

    The XADC has programmable alarms so, again, I highly recommend using that feature for any Series7 project work and monitoring vital signs for distress. It's quite easy to implement the XADC primitive and send readings out from a UART or to an LCD periodically with minimal logic for HDL coding effort.

    Also good point, I will keep this in mind. Thanks.

  5. Hey guys!

    Just got my new AWESOME Genesys ZU board! Sadly, my heat sink has just fallen off. The little yellow square piece was not seated fully and when I went to press it down, the whole thing popped off! Nice to see that gleaming Ultrascale+ chip haha, but I would like a working heat sink :)

    Is there a replacement part number for this? I need the sticky thermal pad stuff (which I am assuming is generic?), and the  yellow clip.

    Thanks!

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