dmeads_10

Members
  • Content Count

    8
  • Joined

  • Last visited

Everything posted by dmeads_10

  1. gotcha, thanks for the thorough answer. Yes okay, sounds like it would work. I havent spent any time with larger scale FPGAs, and I was just concerned that it would take like 1 or 2 hours to synthesize and implement a design. Sounds like it wont unless its reeally big. and yes I use up the synthesis time to do other things as you mentioned like answer emails and do calculations. Thanks for the advice :)
  2. Hi all! I am thinking of purchasing a genesys 2 Board which has a kintex-7 part on it. I have 3 FPGA boards (started with a small lattice board, then a medium altera board, then got a new laptop and a zynq board) and want to move up significantly from the Arty z-7 (which is still a great board) for some of my projects. The problem is, Im wondering if some FPGAs are too much for some computers with not enough resources? specifically Im worried about synthesis and implementation time. If you put the same design on different sized chips, does the larger chip take longer to synthe
  3. Solved: https://forums.xilinx.com/t5/FPGA-Configuration/ZYNQ-XCZ7010-single-port-bram-max-speed/m-p/1070563#M16006
  4. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and sour
  5. Hi all trying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream. [DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logi
  6. Hi folks! New to zynq and programming in C. I have some code that I have written trying to get an led to turn on when a switch on my arty z7-10 board is pressed. It builds okay in SDK but doesn't execute. Can anyone help me trouble shoot please? #include "xparameters.h" #include "xgpio.h" #include "xil_printf.h" #define LED 0x01 #define SWITCH 0x01 //connects bit 0 of gpio channels to led and switch #define GPIO_EXAMPLE_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define LED_CHANNEL 1 #define SWITCH_CHANNEL 2 //defines the channels they are on XGpio Gpio,input, output; int
  7. hi @jpeyron! Yes u found the zedboard tutorial on another forum post and it worked for me! thanks!
  8. Hello All! I just received the arty z7 board yesterday, but I am having immense trouble getting the PL to load a switch-to-LED solution from the flash. I don't want to give up, and I have spent the entire day trying to solve my problem reading other forums, but I still cant figure out how to do it. I just started FPGAs, and have moved up from the lattice tools, so go easy on me this is what I have done so far to try and solve my problem: -I created a Verilog file that makes the LED turn on when the switch is on. -I created a constraints file from the ar