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Everything posted by dmeads_10

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  2. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v
  3. Hi all trying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream. [DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: io5_tri_o[0], LED4_tri_o[0], LED1_tri_o[0], switch_tri_i[0], and BTN1_tri_i[0]. I don't even have these ports in my axi gpio when I click on it. here is my block diagram and constraints file: ##switch set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { switch }]; ##led4 set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { LED4 }]; ##led1 set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { LED1 }]; ##BTN1 set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { BTN1 }]; ##io5 set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { io5 }];
  4. Hi folks! New to zynq and programming in C. I have some code that I have written trying to get an led to turn on when a switch on my arty z7-10 board is pressed. It builds okay in SDK but doesn't execute. Can anyone help me trouble shoot please? #include "xparameters.h" #include "xgpio.h" #include "xil_printf.h" #define LED 0x01 #define SWITCH 0x01 //connects bit 0 of gpio channels to led and switch #define GPIO_EXAMPLE_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define LED_CHANNEL 1 #define SWITCH_CHANNEL 2 //defines the channels they are on XGpio Gpio,input, output; int main(void) { int Status; int SWITCH_data = 0; /* Initialize the GPIO driver */ Status = XGpio_Initialize(&Gpio, GPIO_EXAMPLE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("Gpio Initialization Failed\r\n"); return XST_FAILURE; } XGpio_SetDataDirection(&input, SWITCH_CHANNEL, SWITCH); XGpio_SetDataDirection(&output, LED_CHANNEL, LED); while (1) { SWITCH_data = XGpio_DiscreteRead(&input, SWITCH); XGpio_DiscreteWrite(&output, LED, SWITCH_data); /*i think that the third column is the data to write to output.*/ if(SWITCH_data == 0b0000){} //do nothing else if(SWITCH_data == 0b0001) xil_printf("switch pressed\n\r"); } xil_printf("Successfully ran Gpio Example\r\n"); return XST_SUCCESS; } Also I have my constraints file written correctly, and I have attatched a picture of my block diagram. Thanks!!
  5. hi @jpeyron! Yes u found the zedboard tutorial on another forum post and it worked for me! thanks!
  6. Hello All! I just received the arty z7 board yesterday, but I am having immense trouble getting the PL to load a switch-to-LED solution from the flash. I don't want to give up, and I have spent the entire day trying to solve my problem reading other forums, but I still cant figure out how to do it. I just started FPGAs, and have moved up from the lattice tools, so go easy on me this is what I have done so far to try and solve my problem: -I created a Verilog file that makes the LED turn on when the switch is on. -I created a constraints file from the arty z7 schematic - I programmed the PL ONLY using the hardware manager and the .bit file I wanted to boot this program from the flash, so I then did this: -created a basic block design and generated a bitstream -exported and opened the SDK, as well as created the fsbl file. -got a working boot image, and was able to successfully erase the out-of-box demo. The problem was that the switch to LED code that I wrote and verified doesn't load from the flash. I tried just programming with the hardware manager and the bitstream file, but again nothing happened. keep in mind the switch/LED was working BEFORE I generated the bitstream file with the block design HDL wrapper. (it worked with just the Verilog code for the switch/LED) I tried instantiating the switch/LED code in the block design HDL wrapper, but that didn't work. I thought instead of using the block design HDL wrapper as the top module, I would try the switch/LED code as the top module. This didn't work either. I know that you need to create the block design for the fsbl which is used to program the flash, but how can I get my code for the PL on the flash too? is this a problem with my constraints file? or is there a way to merge the code I want on the PL and the wrapper so the program will load from the flash? thank you! -Dom