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  1. Hello, I am trying to run simulation with design_wrapper(from IP block design including clocking wizard and two custom modules). At clocking wizard, Input is sys_clock(MMCM, single ended, 12MHz, target board : cmod A7 35T) output clock frequency( setting : 40MHz) with no reset, no locked port. When I run simulation with testbench, the sys_clock waveform was shown, but output clock doesn't show. I think two things are weird. first, clock_out1's frequency is to low. (The expected value should be at least 3 times faster than clk_in1) second, clock_out came out just o
  2. Hello, I have a trouble with Verilog module in IP block design. xdcrid_ is my main module which has a state machine and iobuf module is for a inout port(red wire). To notice the current_state (state machine), I attached the leds for each state's output. In one state, xdcrEN(Green wire) get outs from the xdcrid module and this is for 'oe(enable)' signal for following module(iobuf). The state machine works well(I checked the leds for each state as desired) but outp(pupple wire) doesn't get out so that xdcr_ID doesn't work as input signals for main module. I have no idea of what i
  3. @[email protected], I am using Cmod A7 (ARTIX-7). I am not using microblaze now, because I am testing only clock part. My purpose is making 40MHz(differential mode) with 100MHz external oscillator(differential) (this is cmod A7's reference manual) Thank you. Park
  4. Thank you for your advice, but even when I followed your tips, the result was same(failed). Now I wonder if the cause of this problem is local power. The local power supply has only 3.3V, 1.8V and 1.0V. And there are no 2.5V power. So LVDS_25's 2.5V seems like not generatred. I suspect this is the cause. I'm curious about your opinion. Thank you. -S. Park-
  5. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34)
  6. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin
  7. Hello, I bought new nexysvideo board. I read the 'important' message "press reset cpu button before turn off the board power", however I turned off the board power without pressing 'cpu reset' button by mistake. Therefore, board seems like it does not works. When I turn on the power, heat sink has no heat and OLED is turned off. Also when I toggle the switch, the LED doesn't turn on/off (remain off). Is there any solution to resolve this problem? If no, how can I repair this board? thank you.