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About jzaugg

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  1. Hello amkichu, I know it has been a long time between my comment and your previous questions. I recently fixed these issues with a friend of mine when we did a few changes: 1) Make sure you Input buffer your clock from the FPGA or the sys_clk_pin. This would look like: IBUFG inputClkInst(.I(FPGA_CLK),.O(clkFPGA_bufd)); 2) If you have multiple clocking wizards, feed in the previous output clock through a normal buffer like this: BUFG bufg_300MHz(.I(clk_300MHz),.O(clk300_bufd)); Then you can bring in the bufd clock as the input into your other clocking wizard. (Make sure