skylape

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  1. skylape

    Dividing in Verilog.

    Would something like this work https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf ? It is a IP wizard from xillinx.
  2. skylape

    Dividing in Verilog.

    Hello guys, I have a question regarding dividing operation in FPGA(Verilog). Given that I cant use "/" operator, what are the method to divide when the two operands are 16 bit register and when one is 16 bit register and one is a constant? Also is there like a quotient and remainder register like those in AVR? Thank you.
  3. @jpeyron Here is the compress srcs file. Again thank you so much for this. PWM_5MHz Trial 2.srcs.zip
  4. I did make the testbench file and run the simulation. The signal Im getting on it is perfectly good. I think that the clk routing causes the timming error which subsequently makes the board skipping beat. Maybe the clock got skewed big time?
  5. Good morning @jpeyron, During simulation, I couldnt identify the issue, everything runs fine. Atm, I could not see the reason why my code have timing errors in it. The code doesnt seems to be complicated to create some routing issue imo. I think the issue rely in the PLL I create. Any recommendation to fix this ?
  6. Hi @jpeyron, Thank you for the solution, I was able to generate bitstream but there is a Timing problem that Im not familar with. I suspect that the Timing problem is why when I hook up the board to the oscilloscope, I wasnt able to trigger the pulse and I noticed that the device was skipping pulse. Do you have any suggestion regarding this? P/s: The attachments are the timming error summary and the schematic for the design.
  7. Since I only a highspeed clock and nothing else for the moment, my clk wizard only have clk_in1 and clk_out1, so I removed the .locked() from your example. and I tried to run the code again and it still failed to compile. Can you help me take a look into it? `timescale 1ns / 1ps module top( input CLK, input fastClk, output pwm_out1, output pwm_out2, output pwm_out3 ); clk_wiz_0 clk1 (.clk_out1(fastClk),.clk_in1(CLK)); pwm pwm_output1 ( .clk(fastClk), .i_duty(10), .pwm_out(pwm_out1) ); pwm pwm_output2 ( .clk(fastClk), .i_duty(45), .pwm_out(pwm_out2) ); pwm pwm_output3 ( .clk(fastClk), .i_duty(80), .pwm_out(pwm_out3) ); endmodule The below attached pictures is my error codes
  8. Do I need to include this at the end of every instance I create? Because in my top.v I have total of 4 four different instance ( pwm_output1, pwm_output2, pwm_out3 and the clk_wiz one)
  9. Hello everyone, I am facing a problem create an instant of the PLL I setup from the Clocking Wizard. My goal is to provide my PWM module a much faster clock than the 100MHz one. I am extremely new on verilog programming (I know nothing of this stuff yet lol). My current code throw my 16 errors code that I know absolutely nothing about. Any helps on this would be greatly appreciate. Thank you reading P/s: The below text is my top module. module top( input CLK, input fastClk, output pwm_out1, output pwm_out2, output pwm_out3, wire rst, wire lck ); clk_wiz_0(.clk_out1(fastClk),.reset(rst),.locked(lck),.clk_inl(CLK)); pwm pwm_output1 ( .clk(fastClk), .i_duty(10), .pwm_out(pwm_out1) ); pwm pwm_output2 ( .clk(fastClk), .i_duty(45), .pwm_out(pwm_out2) ); pwm pwm_output3 ( .clk(fastClk), .i_duty(80), .pwm_out(pwm_out3) ); endmodule