okonomiyonda

I'm new to Zynq and trying to get DDR3 working on my Zybo Z7-20, and I'm having some issues. When trying to do reads, I do think m_axi_arready is high indicating the slave can take requests, but I never get any responses back on the read data channel. If I validate the design, I get two weird messages. First is a warning about two unconnected address segments, and the other says that interface pin m_axi is not connected to any clock pin, which is weird because I don't have anything in my RTL file called m_axi General setup: I am created the Zynq in block design view, ran configure to set it up for the Zybo, and enabled high performance slave HP0. I then take my top level RTL module, which contains a test for the simple AXI master I wrote, and import it into the block design view. Finally, I hook up the AXI ports of my RTL module to HP0, and hook up the clock to the sysclk defined in the constraints file. See attached file for reference. Assumptions: 0) I don't need MIG. AFAICT, MIG is only needed when you need to generate soft DDR controller IP, and not when you have a hard controller like in the Zynq 1) the "correct" way the use the PL and PS together is to instantiate the Zynq in the block design, and then add an instance of my top level RTL module to the design. I saw some people do the opposite, and instantiate the Zynq in their top level RTL module, but I didn't look into how to connect some of the many ports I didn't recognise 2) I can have my RTL module take in the external sysclk, and also output it as the AXI clock S_AXI_HP0_ACLK 3) I can directly hook up my AXI master to HP0 without needing any fancy other things inbetween. See attached image 4) I assume the PL view of the memory space wants to match the address map in ug585-Zynq-7000-TRM.pdf. That is to say DDR seems to go from 0x0008_0000 ~ 0x3FFF_FFFF. The test read address I am using is 0x0010_0000. I see there is an address editor and address map in Vivado, but I've not yet worked out if I need to mess with that for this test 5) I don't need to (at first) mess with S_AXI_HP0_FIFO_CTRL. But it might be useful for simplifying my master later on 6) I assume AXI3 (memory mapped) is what I want for this board So that's about it. It could very well be a stupid bug in my AXI master, but I wanted to check to make sure the above assumptions were valid. It could also be my inability to use Vitis. And since I am new to Zynq, I'm not yet sure how to simulate anything in Vivado when the PS is involved, especially DDR stuff. I am also not sure how HW debug works in Vitis, or if there is some way to debug hardware like normal in Vivado. I apologise if this is a silly question, but either my googling skills have atrophied, or there really isn't a single example/tutorial on how to use Zynq DDR from RTL on the whole internet. So yeah, I probably am just failing at searching, but everything seems to involve only the PS side, or if it did involve PL, it was only AXI IP and no RTL.

Super late on this, but I am posting just in case anyone reads this in the future. AMP3 does indeed have an I2C config mode, but it also has a simple mode that requires no configuration aside from setting some jumpers. You pass it a few clocks, and the I2S serial data, and its off you go. No I2C required

I'm just getting started with FPGAs, Arty, and Zynq, so I apologise if this is a beginner question or what I'm saying doesn't make total sense. I'm trying to figure out how to read/write DDR and use the UART from the FPGA side with no involvement from the CPU/PS. I've seen Vivado tutorials where you connect the FPGA over AXI and have the CPU sit in a while loop and printf to the UART. I've seen Vivado tutorials where the CPU sits in a while loop, waits for AXI data or interrupts from the FPGA, reads data from memory, flushes the cache, and sends the data to the FPGA. What I can't seem to find is any examples of the FPGA directly talking to DDR and UART. What I know so far: Starting with the image here, it looks like the PL side should be able to talk to DDR and UART over the AMBA interconnect through AXI ports. And indeed, the docs say "cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory" which at least makes me think DDR should be accessible to the FPGA via AXI DMA without PS involvement. I just can't find an example of what I need to do in Vivado to get this hooked up. Separate question: It looks like the PS has a direct connection to DDR that doesn't go over AMBA, so I am wondering what has priority in DDR access, and what the approximate order of magnitude speed difference between CPU uncached direct access and AXI DMA access from the FPGA would be. Maybe the picture is different for the UART, where I see "the peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space". Again, it looks like both the PL and peripherals are connected to the AMBA interconnect, albeit both as slaves. It also seems that peripheral control registers are only accessible in the processes memory space, but if I can rely on the default reset values, maybe that's not a problem? So the TL;DR version is Is it possible to read and write DDR from the FPGA without PS involvement? Can I use the UART from the FPGA without PS involvement? Are there any good samples out there I could reference?