amb5l

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  1. Like
    amb5l got a reaction from [email protected] in new Nexys Video example designs   
    @[email protected] @zygot Quick update: the Xilinx clock domain crossing macros work fine and I have eliminated the timing exceptions. Thanks for your input.
  2. Like
    amb5l got a reaction from JColvin in some Nexys Video VHDL designs (HDMI, audio)   
    I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project
    I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  3. Like
    amb5l reacted to zygot in new Nexys Video example designs   
    @amb5l,
    You might want to consider posting this to the Digilent Project Vault, where it belongs. By posting it to where lots of FPGA related questions are posted every day your visibility will disappear making it invisible to most visitors. Just a thought.
  4. Like
    amb5l got a reaction from [email protected] in new Nexys Video example designs   
    Hi all,
    I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project
    I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
    Grateful for any feedback.