amb5l

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About amb5l

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  1. @[email protected] @zygot Quick update: the Xilinx clock domain crossing macros work fine and I have eliminated the timing exceptions. Thanks for your input.
  2. I have discovered the xpm_cdc_handshake macro ("Bus Synchronizer with Full Handshake") which appears to be a well sorted way to do what I want (to move parallel data from a slow to a fast clock domain, without consuming FIFO resources). I'll try it and report back.
  3. @[email protected] Understood. You're not wrong - I've used FIFOs, in fact I wrote my own hairy controller for an async FIFO on a Virtex-1 about a million years ago; gray coded pointers etc; it was the only way I could get that generation of parts to move data @ 100MHz. I can't remember why I didn't use a FIFO in this design but - given the glacial data rate - the design does function just fine with double syncing between the domains. I think of the arrival of an audio sample in the FIFO as being a bit like an occasional button press - and by the time the FIFO ready status has ripped through the synci
  4. I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline.
  5. @zygot Thanks. I'll go and find it and do as you suggest.
  6. Dan, I appreciate your feedback. audio_axis.vhd moves audio samples from the CPU clock domain (100MHz) to an audio sample rate interface (48kHz). Specifically, it pulls the samples - one at a time - from the AXI Streaming interface of a FIFO that is coupled to the MicroBlaze CPU. The low audio sample rate means timings are very relaxed and it all seems to work fine. Tests on hardware work OK; I've listened to classical music for hours (with the modulation disabled!). I will look at an exhaustive test; the simulation testbench is very basic and does not yet support automated testing.
  7. Hi all, I've developed a few audio and video example designs for the Nexys Video in VHDL and posted them here: https://github.com/amb5l/tyto_project I am planning to expand on the HDMI IP to make it more general purpose, and add DisplayPort eventually. There is more stuff in the pipeline. Grateful for any feedback.