NotMyCupOfTea

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Everything posted by NotMyCupOfTea

  1. Dear @Anji and @hawk20002000, Sorry for the absence of response... I am sorry that you couldn't find the project any more... however I'm no longer able to upload it as my internship is finished and I don't have access to it any more. However, I can provide a very detailed guide that explains how to build the blinky project. Concerning @Anji's problem, I don't think this might help though as you already are able to communicate back and forth with the FPGA. However, I have seen that it is indeed possible to upload files in the board memory to read them. Maybe someone else her
  2. Dear Zygot, Thank you for your answer. I didn't mean to upset you but as I have already tested for endianness and am using verilog, I wonder wheter the procedure you described allows to test something else. On top of that, I have been working on FPGA for only 4 months and am still very unexperienced ==> i.e. I was not able to implement your suggestion and have no one near by who can help me understanding what you wrote. This is why I share the code. Now, the question was what other problem can we think of. Thanks for your help,
  3. Hi Zygot, Thank you for your answer! However, I don't think the problem comes from endianness... As you can notice on the pictures of the previous post, the number of steps M and N are correctly transmitted to the board. Now I mght be wrong but I would expect a endianness problem to affect all the values sent between the PS and PL. Furthermore, I've also tested to compile a project where the PS is included but "not working". meaning that the parameters remained hard coded in the PL. and it also doesn't work. So I would think that the problem doesn't come from the communicat
  4. True, I'm sorry... The project is meant to control Galvanometric mirrors to swipe a laser for a OCT microscopy system. These mirrors can be oriented in space by applying a voltage to their poles and by this means orient the laser beam where needed to proceed for the imaging. Now, acquiring an image requires to move the laser beam over the surface you want to acquire (for instance following the coordinates (0,0) - (0,1) - (0,2) ... (0,M) - (1,0) - (1,1) ... - (M,N)). The output is then rescaled and sent to a DAC. Please see attached file to see what it looks like (please not
  5. Dear All, "I'm working with Vivado 2018.3 and a Zybo Z7020 board" I write here because I have a very strange problem in a project that I have been developing in the past months. Namely, I've been writing a verilog code to run on a Z7020 board. This code takes user input as parameters (that are hence hard-coded) and everything works fine with this project (no errors or not understandable warnings...) Now, my job is to make sure that these so-colled parameters can be changed through a serial connection from a laptop. Hence, I've packaged my module in an IP and connected it to
  6. Hi everyone, I am currently working with a Zybo Z7010 board on Vivado 2018.3 and am trying to implement a memory access in both reading and writing modes. More precisely, I'd like to enable the user to enter a number of coordinates that define a random waveform (sine table...) and to store it somewhere so that the PL can access it in reading mode and display it through a DAC. Please note that it is essential that the reading process is fast for further applications. Now, have been reading many things but I'm a little confused about the "different types of memories that exist". I
  7. Dear all, I'm using Vivado 2018.3 and a Zybo Z7010 board. I have finally finished my project (I actually owe this forum much), and I am now trying to use the board without having to open nor Vivado neither the SDK. Basically, I know that I can program the QSPI flash memory of the board so that the program can run without having to upload it. How this works is still unclear, is switching from JTAG to QSPI enough or should I do something on Vivado? However, I am also using the Zynq processor which runs an application that I start from the SDK. Can I avoid opening the SDK?
  8. Dear @jpeyron, Your help has been once again decisive to the success of the project I'm working on. Thank you ! For those who are interested, please find here the files for the blinky project I was able to build. From this point, it is only a matter of minutes to adapt it to your own customized project. Best regards to all, NotMyCupOfTea
  9. Dear @jpeyron, Thank you very much for your answer! I am now one step closer to achieving what I'm up to. I have managed to create my custom IP block which has one parameter (which led to switch on) and one output (the 4-bit signal connected to the leds). Now, I have set the parameter to 2 while building the project and the correct led is turned on. Is there a way to modify this parameter from an SDK application? Thank you, NotMyCupOfTea,
  10. Dear @jpeyron, Thank you for your answer. I already had the Digilent Board files installed but it looks like they are used correctly only if you select the board (and not the part) in the "Creat a Project" wizard... When I did that, everything worked as I wanted, the Hello World project as well. Concerning the "Blinky" project, I don't quite understand... is it enough to have the blinky.v file in the same project directory? I couldn't manage to package it as an IP... By the way, I have been following this tutorial until exercise 5 (where I am stuck because I don't know how
  11. Dear All, I have been working today and unfortunately did not manage to work out your instructions @jpeyron. Here are a few thoughts: - When I want to use the "Hello World" template, it says that I have no UART in my design and that I can't use it. I therefore went back to the design ==> customize IP and add UART1 port in the "MIO Configuration". This seems to solve the matter... - When I manage it through to point 6, running the application give me the following error : AP transaction error DAP status f0000021. My guess lies in a comment line of the Hello World that specifie
  12. Dear All, Thank you for your clear answers. @vicentiu : I think I understood the difference between bare metal and linux enbedded in the PS and as I don't need to do very complex operations in the PS I think bare metal will be enough for this time. (Though, I might change my mind in the future...) @jpeyron : Thank you so much for your detailed guidelines! I will follow those steps during the week-end but I won't be able to test it before Monday as I don't have the board with me. Starting with this simple project seems a good idea, now I have a question about step 4 for the proje
  13. Hi @vicentiu, I don't really know the difference between "Linux" and "Bare metal" and am sorry if I have posted the question in the wrond repository... As I don't know the difference, I can't tell yet which of these options I'd prefer... Feel free however to move the discussion where it is most appropriate (or if I have to do it please let me know). Thank you,
  14. Dear All, I have currently finished a PL program for signal processing and hardware controlling on the Zybo Z7010 board. Now, I want to ensure that some parameters can be easily modified by the user on a computer. Thus, I would like to use the USB -- micro-USB cable to instaure a communication between the user and the board. After some reading, I understand that I have to use the PS if I want to go through the micro-USB UART port (I have not yet used the PS in my project...). Hence, I need two things: - Instantiating the UART interface and writing the C/C++ script to e
  15. Hi @jpeyron, Thank you for your answer. If I understand the thread you pointed out well, I need to build an external low-pass filter. Is it absolutely necessary ? Isn't there a way to use built-in components to do so ? If not, I will try implementing the filter. Bye,
  16. Dear Jon, Thank you for your answer. I have tried to instantiate de VHDL code from @hamster in my program as follows, after having added a VHDL source from the "add source" menu: pmod_da3 myDAC ( .clk(clk), .CSn(jc[0]), .LDACn(jc[2]), .SCLK(jc[3]), .SDAT(jc[1]), .level(dout) ); Where jc[0] is the correct CS pin, jc[1] data pin, jc[2] LDAC pin and jc[3] clock pin. This seems to work quite well, until I input a signal of 10kHZ. I have the same clock parameters as in @hamster XDC file. I think the problem could come from th
  17. Hi everyone, After having succesfully managed to use de XADC of the Zybo Z7010 board as explained in this post, I am now trying to use a DAC Pmod (reference and documentation here). After having checked the documentation, I have tried to write the SPI connection to the DAC (please find the verilog file and simulation in the attached files). Note, that I have decided to set the l_dac signal to 0 to enable continuous output to an oscilloscope. The simulation seems to run well to me and to be in accordance with the documentation, however, the result is not satisfactory. I
  18. Hi jpeyron, Thank you very much for having helped me, it works fine now ! Problem solved !
  19. Hi jpeyron, Thank you for your answer ! I have uploaded the TOP verilog and the XDC file on Vivado and synthetized it. At this point it told that xadc_wiz_0 was not found. How should I include the xadc wizard ? I have tried to click on "add source" but I couldn't find the file. The button "Open block design" is unaccessible and I am not sure that creating a block design is necessary. For the time being, I have uploaded the directory named xadc_wizard_0 from the project that can be found here : https://github.com/Digilent/Zybo-Z7-10-XADC/releases/download/v2016.4-1/Zybo
  20. Hi, Problem : I am new to FPGA and I would need to understand how to read an Analog input through the XADC to analyze it on the board and then be able to accordingly output a trigger for other machines. One simple thing that I would try to do for the time being is to read in the analog signal and wire it to a led so that I could effectively see the code is working. How do I do that ? Finally, one extra constraint is that I have to limit as much as possible the use of the Zynq processor (I'm not really sure this is achievable, please excuse my lack of knowledge).