The_YongGrand

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  1. Hello @jpeyron, I have successfully uploaded this bitstream into the Cmod-A7! :) Writing a simple tutorial now for reference! :)
  2. Hey there @jpeyron, just tried following the instructions, and got the bitstream! Didn't know that the wrapper is important to that particular toolset. I'm gonna try to download it into the A7 and report the results tomorrow, as it's late for today! If all that works wonderful, I'm gonna write a tutorial here and on my page too.
  3. Hello @jpeyron, thanks for the responses. I'll try that the next day as I'm away from the desktop now and will report whether it works or not. 😀
  4. Hello @jpeyron, thanks for the hint. I attempted this, and the bitstream got compiled. However, I would like to work on the "Block Design" and get the bitstream to be compiled, but failed. Since I previously worked on Quartus 2, the "Block Design" format will be more familiar with me, but all the tutorials I have searched did not address a simple Verilog LED blinking with the format. Either it is all with a Microblaze or a very complicated project. Here are my attempts: 1.) Create new project. 2.) IP Integrator -> Create Block Design. I named it "system". 3.) Dragged the "System Clock" (in that picture) onto that blank diagram area: 4.) "Add module", put my example Verilog file, which is already on the first post. Then connect all the wires: 5.) Synthesis and Implementation passed, but not Bitstream. It complained about this: That IO port at the right "led[1:0]" is from the constraint file. I have even added this in the constraint file: What I do not understand is: 1.) Which IO the "reset" and the "sys_clock" port on the clk_wiz_0 is from? Is it defined? I saw buttons and the sysclk from the constraints file, but I don't get to see how it is connected to the block. 2.) the "clk" is connected to "clk_out1", and does not involve IO at all. It is wired internally, but toolchain flagged an error on this one? 3.) Same as (2), the led[1:0] is from the constraints file, and the error as well. I could easily do this in Quartus 2 without errors and I'm wondering if there are anything else I missing over there. I got this little Cmod-A7 because it has more features than my old generation Cyclone2.
  5. Hello there, I just got myself CMOD-A7 with Xilinx Vivado (latest), and I wanted to try to start with the simple LED blinking example. However, it never get past compiling at the Implementation or the Bitstream stage. Here are my attempts starting from no. 1 to the end: 1.) Create new project. 2.) Added the CMOD-A7's constraints (cmodA7_B.xdc), and commented out the clock part and some GPIO ones: 3.) Using the Clocking Wizard, I have created the block with 100M and 12M outputs (as an example, based on this: https://forum.digilentinc.com/topic/9419-using-vivado-ip-clocking-wizard-with-the-cmod-a7-35t/) The outputs are named clk_100 and clk_12 for now. Inputs is named clk_in, and the "sysclk" come from the constraints file. 4.) Generated the clock module, "out of context per IP". 5.) After generating, opened the clock module's VEO file and copied that implementation part: 6.) Pasted and modified it onto the example verilog file: 7.) Synthesis can be completed, but not implementation. The error: Are there any steps I missed out so far? I could compile okay on a Quartus 2 and generated a clock module at an instant there, and I'm curious if I could do the same on Vivado? Something like this: Hope I can get a good guidance on this. Thanks.