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  1. Hi @jpeyron,, many thanks for the support. Unfortunately your bitstream file does not work on my board. I also generated the bitstream from your project. No signal is detected on my screen. I am frustrated because I can't understand why. However, I was able to get the board working with this project that I found on Github: Best regards.
  2. Dear @jpeyron, To summarize my problem: On nexys video: Clocking Wizard: PLL and RGB2DVI:PLL ==> bitstream is generated but no signal detected on screen and ILA core clock stopped Clocking Wizard:MMCM or RGB2DVI:MMCM ==> unroutable placement error message On zybo z7-20 : Clocking Wizard: PLL and RGB2DVI:MMCM ==> bitstream is generated and project works perfectly. Video is streamed on the screen. I am without understanding why the Nexys Video does not work. PS: I am not sure if it is relevant but I am using Vivado 2018.3 on a Windows 10 machine. The RGB2DVI version is 1.4 and DVI2RGB version is 1.9 Thank you.
  3. Dear @jpeyron, thank you! The Nexys Video HDMI project works as well as the default demo from the board. Regarding to the simple pass through buffer, when the clocking wizard and RGB2DVI is both configured as PLL the bit-stream is successfully generated. I am even able to see the ILA core with a message "no content". However, when I press play the "ILA clock stopped" message is shown and no signal detected is displayed on the screen. Otherwise, if the MMCM is setted instead in the DVI2RGB, the bad routing message is displayed and I am not able to generate the bit-stream. I really need this simple project working instead a larger one such as the demo that comes available from the link you posted. I am curious why this project, properly re-targeted to a Zybo Z7-20, runs without any problem. One more time, I do appreciate your support.
  4. Interesting that I re-targeted the project to a Zybo Z7-20 and the project runs without problem when RGB2DVI is marked as PLL and I can reproduce the screen of my laptop on the monitor at 1080p.
  5. Hi everyone, thank you for the explanations and details already here. I have a Nexys Video that I received today and I have the following diagram for the passthrough buffer. My clock wizard is setup to 125Mhz. DVI2RGB is for 1080p clk >= 125MHz. Same for RGB2DVI. My problem is: If I set RGB2DVI as PLL I got the following error: [Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core. Otherwise, if MCMM is setted, than I get this error: [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/I] > Could anyone, please help me? Best regards, Carlos I have the following xdc constraints: [Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core. ### This file is a general .xdc for the Nexys Video Rev. A ### To use it in a project: ### - uncomment the lines corresponding to used pins ### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock Signal set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## System Reset set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { rst }]; #IO_L20N_T3_16 Sch=btnc ## HDMI in set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p create_clock -period 6.734 -waveform {0 3.367} [get_ports { hdmi_in_clk_p }]; set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_in_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0] set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0] set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1] set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1] set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2] set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { hdmi_in_data_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2] ## HDMI out #set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_out_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0] set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0] set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1] set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1] set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2] set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2] ## Configuration options, can be used for all designs set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design]