Takemasa Tamanuki

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  1. Hello again, My problem which I could not implement 100MHz-clock into RTL module is solved. I did newly implement the Clocking-wizard from IP-catalog and add (and revise it as appropriate ) a clocking-wizard-template into V-file as following. ---------------- module Clock_testV1(input sysclk, output pio1, output pio2); reg [0:0] CLK1; wire reset; wire clk_out1; wire locked; always @(posedge clk_out1) begin CLK1 <= CLK1+1'b1; end clk_wiz_0 ( .clk_out1(clk_out1), // output clk_out1 .reset(reset), // input reset .locked(locked), // output locked .clk_in1(sysclk)); // input clk_in1 assign pio1=clk_out1; assign pio2=CLK1; endmodule --------------- 50MHz (and 25MHz) waveform was confirmed by Analog discovery 2 (Oscilloscope displayed waveform is limited by the band-width of AD2 (30MHz).). I would appreciate your comments if my clocking-wizard implement procedure is correct. Fig. 1. Measured waveform (C1(yellow, pio1): 50MHz, C2(blue, pio2): 25MHz).
  2. Hello there, I am trying to introduce 100MHz-clocking into RTL-module instead of the 12MHz-sys-clock. I have made a circuit with connection of [“clk_out1”: Clocking Wizard output] and [pio46: RTL input] (see Fig. 1) and check the pin-out-waveform by the following HDL-statement. (Here, I chose the pio46 as a clock-route since it is clock-dedicated-pin of ”P_MRCC”.) --------------- module Clock_testV1( input pio46, output pio1, output pio2 ); reg [0:0] CLK1; always @(posedge pio46) begin CLK1 <= CLK1+1'b1; end assign pio1=pio46; assign pio2=CLK1; endmodule -------- However, the pio1 (as well as pio2) output did not show pulsed-waveform (but 3.3V continuous DC output, see Fig. 2. C1: yellow, pio1, C2: blue, pio2)). On the other hand, If I replace the “pio46” to “sysclk” in my HDL-statement, it works normally corresponding of 12MHz-clock (see Fig. 3. C1(yellow, pio1): 12MHz, C2(blue, pio2): 6MHz). I would appreciate if you could provide comments to solve (about introduction 100MHz-locking into RTL-module) this issue. PS: I also referred the following sites, but I could not solve my issue. https://forum.digilentinc.com/topic/5325-vivado-clock_dedicated_route/ https://forum.digilentinc.com/topic/18479-cmod-a7-vivado-2019-cannot-get-past-implementation/
  3. My requesting about to know the “storing the configuration program to Flash-memory” is solved by learning the “2. Creating Program File” of “Cmod A7 Programming Guide”. So, no need your answers for the Q1 and Q2. I'm sorry to interrupt you.
  4. The Q2 statement is revised. [Wrong] Please let me know, How to show this pop-up? [Correct] Please let me know, How to show this “SREC SPI Bootloader” Templates? Actually, I am using a “Xilinx SDK 2019.1”.
  5. Many thanks for your comments. I started to learn and handling of the CMOD-A7(35T) and the “blinky.v” is successfully worked on my CMOD-A7 (on Vivado 2016.4) based on the “Getting Started with Vivado”. Next, I am trying to store the project by referring the “How To Store Your SDK Project in SPI Flash”. https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start Q1: I did the “0. Compress Bitstreams (Optional)” (<-- check the “-bin_file*[V]” and set “Enable Bitstreem compression [TRUE]”), > 0.6) Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. > Select [Generate Bitstreem] and a window might pop up asking you to save your XDC. If so, give the XDC a name and save it. Your bitstream should start generating afterwards. However the “window might pop up asking you to save your XDC” is not shown in my window. Please let me know, How to show this pop-up? Q2: On the following section of the “1. Create a SPI Bootloader Application”, > 1.2) Select SREC SPI Bootloader and select Finish. However, the “SREC SPI Bootloader” is not shown on the “Available Templates:”. Please let me know, How to show this pop-up? Thanks, T. Tamanuki
  6. Dear zygot_san, Many thanks for your detail comments. I purchase ordered the Cmod-A7(35T) today and it will be shipped to us tomorrow. BTW, do you have reference FPGA-configuration program of SPI-driving-circuit? I would like to configurate the FPGA as “driving circuit of 8-slaves SPI (MOSI only)”. Also, do you have reference run-program (SRAM table) of the SPI-driver-configurated-FPGA? I would appreciate if you could provide them to me. Thanks.
  7. Dear xc6lx45_san and zygot_san, Thank you very much for your detail comments about the FPGA-module product of Cmod A7 and Cmod S6. Actually, the AD2 is introduced into my existing SPI-circuit-system (8-slaves-SPI (MOSI): 16pcs-DACs are included in the each slave. That is 128pcs-DACs for 8-slaves.) and I am considering to introduce a FPGA into the programmable-control of SPI. Because, I am thinking that we can speed up the program-executing-time by introduction of FPGA instead of AD2 due to eliminate the USB-communication-time on the AD2-case. >> It has built-in PLLs so you can generate any frequency you like. > The CMOD A7 devices have clock management hardware so you can take any input clock and create a lot of different output clocks for your design. In my existing AD2-SPI-circuit-system, I am driving it with clock-speed of 10MHz. For my double checking, the CMOD A7 can create 10MHz SPI_clock (by PLL). On the other hand, the Cmod S6 can not create 10MHz-clock since it has no PLL. Am I right?
  8. I am driving DACs (up to 50MHz clock, 24bit command) using a SPI-bus by AD2 right now and I am trying to drive the DACs by FPGA. This might be basic, but could you tell me the following queries about the products of Cmod A7 and/or Cmod S6. Q1: Is it possible to use the Cmod A7 and/or Cmod S6 as a SPI master (mosi and miso)? If yes, Q2: How many SPI-slaves can we control by the Cmod A7 and/or Cmod S6? (Is it possible to control 8-slaves?) Q3: What is the clock-speed of the Cmod A7 and/or Cmod S6? (Is it fixed clock-frequency? Or variable? 10MHz, 20MHz or 50MHz are possible?) Q4: What is the program language is used for the FPGA program of the the Cmod A7 and/or Cmod S6? (Can I use Python? Or HDL only?) Q5: Can we introduce a “pause (for example 0.01msec, 0.1ms, etc. ) routine” into the FPGA program of the the Cmod A7 and/or Cmod S6?
  9. Hi, Attila_san, Many thanks for your advice. > “Polarity=0, Phase=1” are required specification of my DAC. > (Setting with “0” on the ModeSet looks better than that of “1” for my DAC. Am I right?) In my DAC (“Polarity=0, Phase=1”) case, I understand the iMode setting should be “1”. (I will re-check the DAC-datasheet if “Polarity=0, Phase=1” is correct as well.)
  10. Thanks for your detail comments. Also, please let me know the setting parameter on the dwf.FDwfDigitalSpiModeSet(hdwf, c_int(0)) Is it related to the “Polarity” and/or “Phase”? “Polarity=0, Phase=1” are required specification of my DAC. (Setting with “0” on the ModeSet looks better than that of “1” for my DAC. Am I right?)
  11. Hi, Attila_san, Thank you very much for your comments. Finally, the “Digital_Spi.py” works in my setup with AD2 successfully. One more question, regarding the Clock-Frequency. My setup does not work more than 10MHz (it works at 10MHz, but not work at 11MHz and more) on the “Digital_Spi.py”. (My setup also does not work more than 10MHz on the waveform-application.) Can my setup work at 50Mz with AD2 by optimizing the clock-circuit of my setup?
  12. I am trying to make a AD2 SPI control program by VB. I have referred some comments on this site but I can not solve that. Could you provide some comment for this issue? (or If you can provide me any reference SPI VB-project-program, it is very helpful for me. I will try to custom it for my use.) Thanks,