HoWei

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  1. Hi, I am successfully using the DIOs to control an ASIC. In addition to the control lines I want one DIO to generate a pulse with defined delay and duration - its a enable signal for a short time only. The "DigitalOut_Pulse.py" example does not help, as this is simply switching ON/OFF the DigiDisco, but I need it running. So far I tried different modes (pulse/custom) and counter (init) settings - but I either get repeated signals or no output. With custom mode I can manage to get one rising edge - but not a pulse (rising + falling edge). Can you please provide an example ?
  2. Okay, that explains a lot ! Thanks - so far it is working stable.
  3. Hi @attilla, I found that I do have to set the input buffer size "dwf.FDwfDigitalInBufferSizeSet(hdwf, c_int(nSamples))" to capture the signal. What happens if I do not set this buffer size ? If this buffer size is not set - why does it capture a constant clock signal but not a signal coming at the trigger time ? Can you please explain the difference ? Another question is why it work in WaveformGUI "record" mode, but in the script I need to use "single" mode (which is not available in WaveformGUI ) ? Whats the difference ?
  4. I tried setting "dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalOut)" as trigger source as recommended in : But no success - still receiving all 0s. I cannot even identify the trigger time point. Whenever a continous signal is applied I capture the signal. But a signal starting at the same time as the trigger is not captured ???
  5. Attached please find the script, where I try to capture in record mode with "normal" trigger - I do not capture the expected signal. But the oscilloscope shows that the testsignal on DIN11 is available immediately after the trigger-signal on DIN15 comes. from ctypes import * from dwfconstants import * import math import sys import time import matplotlib.pyplot as plt import numpy as np import digilent as dig ################## #MAIN ################## #init first Digilent device found #and set output voltage to 1.8V dwf, hdwf = dig.initDevice(1.8) time.sleep(0.1) dwf.FDwfDigitalIOReset(hdwf) #get internal clock frequency hzDO = c_double() dwf.FDwfDigitalOutInternalClockInfo(hdwf, byref(hzDO)) print("Internal frequency is " + str(hzDO.value/1e6)+" MHz") cap_trig = 15 # DIO15 Pin39 ################################################################################################# # Configure capture trigger output - will toggle only once before first valid sample is available ################################################################################################# dwf.FDwfDigitalOutEnableSet(hdwf, c_int(cap_trig), c_int(1)) #set to output dwf.FDwfDigitalOutTypeSet(hdwf, c_int(cap_trig), DwfDigitalOutTypeCustom) #Custom type for single edge dwf.FDwfDigitalOutOutputSet(hdwf, c_int(cap_trig), DwfDigitalOutOutputPushPull) #drive output load dwf.FDwfDigitalOutIdleSet(hdwf, c_int(cap_trig), DwfDigitalOutIdleLow) dwf.FDwfDigitalOutDividerSet(hdwf, c_int(cap_trig), c_int(int(hzDO.value/20e6))) # 20MHz dat_cap_trig = c_int(1) # send only one rising edge dwf.FDwfDigitalOutDataSet(hdwf, c_int(cap_trig), byref(dat_cap_trig), c_int(1)) data = 8 #DIO8 Pin32 ################################################################################################# # Configure data output - will send 01010110 ################################################################################################# dwf.FDwfDigitalOutEnableSet(hdwf, c_int(data), c_int(1)) #set to output dwf.FDwfDigitalOutTypeSet(hdwf, c_int(data), DwfDigitalOutTypeCustom) #Custom type for single edge dwf.FDwfDigitalOutOutputSet(hdwf, c_int(data), DwfDigitalOutOutputPushPull) #drive output load dwf.FDwfDigitalOutIdleSet(hdwf, c_int(data), DwfDigitalOutIdleLow) dwf.FDwfDigitalOutDividerSet(hdwf, c_int(data), c_int(int(hzDO.value/20e6))) # 20MHz data_send = (1*c_int)(0x65) dwf.FDwfDigitalOutDataSet(hdwf, c_int(data), byref(data_send), c_int(8)) ######################################## #set DIO output runlength and repetition ######################################## dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # only once ###################################################################################################################################################################################### # Configure DIN data capture ###################################################################################################################################################################################### # set number of sample to acquired by DigiDisco nSamples = int(1000) print("nSamples =",nSamples) # set number of sample to acquire #nSamples = 1200000 rgwSamples = (c_uint16*nSamples)() cAvailable = c_int() cLost = c_int() cCorrupted = c_int() cSamples = 0 fLost = 0 fCorrupted = 0 hzDI = c_double() dwf.FDwfDigitalInInternalClockInfo(hdwf, byref(hzDI)) print("DigitalIn base freq: "+str(hzDI.value)) dwf.FDwfDigitalInAcquisitionModeSet(hdwf, acqmodeRecord) # record mode dwf.FDwfDigitalInDividerSet(hdwf, c_int(int(hzDI.value/400e6))) #400MHz # 16bit per sample format from DIN0..DIN15 dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(16)) #define trigger pin DIN trigDIN = 15 #set trigger source dwf.FDwfDigitalInTriggerSourceSet(hdwf, c_int(3)) #3=trigsrcDetectorDigitalIn see SDK docu # number of samples dwf.FDwfDigitalInTriggerPositionSet(hdwf, c_int(nSamples)) dwf.FDwfDigitalInTriggerPrefillSet(hdwf, 0) #no prefill dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(1<<trigDIN), c_int(0)) #rising-edge on pin trigDIN #dwf.FDwfDigitalInTriggerLengthSet(hdwf,0,0,0) #trying to set trigger mode "normal" autotimeout = c_double() dwf.FDwfDigitalInTriggerAutoTimeoutSet(hdwf, c_double(0.0)) dwf.FDwfDigitalInTriggerAutoTimeoutGet(hdwf, byref(autotimeout)) print("Autotimeout:",autotimeout) psecmin = c_double() psecmax = c_double() pnsteps = c_double() dwf.FDwfDigitalInTriggerAutoTimeoutInfo(hdwf, byref(psecmin), byref(psecmax),byref(pnsteps)) print("AutoTriggerInfo:", psecmax, psecmin, pnsteps) ##################################################################################################################################################### # Activate DIN capture and DIO output ##################################################################################################################################################### # begin acquisition dwf.FDwfDigitalInConfigure(hdwf, c_bool(1), c_bool(1)) print("Starting record...waiting for trigger on DIN", trigDIN) time.sleep(3) #wait some time before triggering # activate the DIO outputs dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) #start the DIO device (non-blocked outputs only) print("Starting data transmission ...") #check successfull acquisition sts = c_byte() while cSamples < nSamples: dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts)) if cSamples == 0 and (sts == DwfStateConfig or sts == DwfStatePrefill or sts == DwfStateArmed) : # acquisition not yet started. continue dwf.FDwfDigitalInStatusRecord(hdwf, byref(cAvailable), byref(cLost), byref(cCorrupted)) cSamples += cLost.value if cLost.value : fLost = 1 if cCorrupted.value : fCorrupted = 1 if cAvailable.value==0 : continue if cSamples+cAvailable.value > nSamples : cAvailable = c_int(nSamples-cSamples) # get samples dwf.FDwfDigitalInStatusData(hdwf, byref(rgwSamples, 2*cSamples), c_int(2*cAvailable.value)) cSamples += cAvailable.value time.sleep(3) # as long as the device are not closed the voltage output is available dwf.FDwfDeviceCloseAll() print(" done") if fLost: print("Samples were lost! Reduce sample rate") if cCorrupted: print("Samples could be corrupted! Reduce sample rate") f = open("record.csv", "w") for v in rgwSamples: f.write("%s\n" % v) f.close() #filter samples by signal fclk = np.zeros(nSamples) dclk = np.zeros(nSamples) datA0 = np.zeros(nSamples) datA1 = np.zeros(nSamples) datB0 = np.zeros(nSamples) datB1 = np.zeros(nSamples) datC0 = np.zeros(nSamples) datC1 = np.zeros(nSamples) datD0 = np.zeros(nSamples) datD1 = np.zeros(nSamples) testData = np.zeros(nSamples) trigIN = np.zeros(nSamples) #filter each signal with logic AND from rgwsamples #and then shift to right end for i in range(nSamples): fclk[i]=int(rgwSamples[i] & 0x01) #fclk=DIN0 dclk[i]=int((rgwSamples[i] & 0x02) >>1 ) #dclk=DIN1 datA0[i]=int((rgwSamples[i] & 0x04) >>2 ) #datA0=DIN2 datA1[i]=int((rgwSamples[i] & 0x08) >>3 ) #datA1=DIN3 datB0[i]=int((rgwSamples[i] & 0x10) >>4 ) #datB0=DIN4 datB1[i]=int((rgwSamples[i] & 0x20) >>5 ) #datB0=DIN5 datC0[i]=int((rgwSamples[i] & 0x40) >>6 ) #datC0=DIN6 datC1[i]=int((rgwSamples[i] & 0x80) >>7 ) #datC0=DIN7 datD0[i]=int((rgwSamples[i] & 0x100) >>8 ) #datD0=DIN8 datD1[i]=int((rgwSamples[i] & 0x200) >>9 ) #datD0=DIN9 testData[i]=int((rgwSamples[i] & 0x800) >>11 ) #trigIN=DIN11 #trigIN[i]=int((rgwSamples[i] & 0x8000) >>15 ) #trigIN=DIN15 #plt.plot(fclk,'b') plt.plot(testData,'r') plt.show()
  6. Hi @attila, I solved my delay-problem by "hardware-hacking" the DigitalDisco device. I connected to the onboard 12MHz XO (next to the FTDI chip) via an resistive divider to reduce the amplitude. This provides a syncronized clock for the ADC. I adjusted my DIO clocksignals to 4MHz - this allows me to capture without any delay time. The only issue remaining is the "normal" trigger in record mode via my python script - but this is already discussed in another toptic/ticket/question. It would be very very very helpful to have a syncronous output constantly running with the same divider and counter options as a DIO. Its just a FPGA - (almost) everything should be possible right ;-)
  7. I tried to set dwf.FDwfDigitalInTriggerAutoTimeoutSet(hdwf, c_double(0.0)), which (according to the SDK docu) sets the normal trigger - but no effect ! How is the digital threshold set for the DIN pins ? On DIN0..9 I do have CMOS Level inputs 0..3V, but DIN15 and DIN11 are from the 1.8V DigiDisco outputs. Could it be that the threshold is too low to detect the high levels for DIN11 ? But why does the DIN15 trigger then ? Edit: It cannot be the amplitude or threshold because I can capture a clock signal with 0.9V amplitude ! Thus leaves the problem that I cannot trigger in "normal" mode in python ! Could you please provide a short example for "normal" trigger in record-mode?
  8. Hi @attila, I have setup a small test comparing Waveforms vs. my python script. The setup is very simple: - DIO39 connected to DIN15 (This is the trigger for the record-capture) - DIO32 connected to DIN11 (this is the testsignal to capture) The DIO39 (blue) shall trigger the record-mode capturing and the DIO32 (yellow) provides some samples. The signal look like this: In Waveforms GUI it is working as expected IF I set the trigger mode to "normal". If the trigger mode is set to "auto", I will always receive 0s - why is that ? In my python script I always receive 0s - what is the command to set the "normal" mode for triggering via SDK in python ? Thanks !
  9. I do use the DigitalDiscovery logic analyzer to capture data from an ADC. I trigger the capturing via a rising edge at DIN15. The timing diagram looks always the same like this: Blue is the trigger for the logic analyzer / Yellow indicates the ADC clock / Red is the sampled data The ADC transmits the data serially (via 2 wires) to the DigiDisco-Logic inputs. After the transmission I decode the data, starting from sample one and plot the ADC sampled data. What I expect is a plot like this - starting with 01010101011111.... What I get is different for each capture as shown below.: - It seems like the trigger or start of capturing has a certain variation or delay. - It is capturing data BEFORE! the trigger signal occurs - I am sampling with 400MHz the DigiDisco DIN channels, this means there are more than 100 samples taken BEFORE! the trigger is coming. Is this delay/variation expected ?
  10. Hi @attila, I do have trouble to understand what your ROM example does. Could you please elaborate in more detail - with words ? What is the advantage of ROM ? The only thing I currently see is, that it uses twice the number of outputs. Does ROM offer the possibility to create a delay between ADC clock and data-clock of >1s ? In my application I found that the ADC requires a stable 10MHz clock for more than 1s until valid data is at the output (it could be also 500ms - I am still debugging this delay requirement). So far I assumed 1ms, because it is enough to lock the PLL - but it needs much more time to stabelize the internal serializer (apparently). [EDIT]: I found that after 10ms of ADC clock the ADC output data are valid - thus a delay of 10ms would solve my problem and I could use the DigiBox in our application (multiple times) ! Is there an internal node/pin/connector in the DigitalDisco that would provide a syncronous 100MHz clock (the internal sample rate), which I could divide down to 10MHz/5MHz/1MHz with external circuitry ? Or would it be even possible to "hack" the internal FPGA to make one channel a constant 10MHz clock ? Ormaybe split the DIO outputs into 2 "banks" to control them independently ? Any ideas would be helpful - even if I void the warranty.
  11. Hi @attila, thanks for looking into it. What do you think about the above idea with "initial counter values" ? So far it is working reliably for me, even if I dont understand why the initial delay with custom dataset is depending on dataset size. Below is a screenshot of the full sequence run once with the correct runlength:
  12. I found another way to create a delay between DIOs: setting the "initial counter value". For ADC clock (DIO 5) I do not set the inital counter --> it starts immediately after dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) For CLK and BUS (DIO0..4) i do set the initial counter to a high value (~10000) --> this ensures the CLK (DIO4) and BUS(DIO0..3) are starting after ~1ms This is working in principle, but I do not understand why the initial delay of the BUS (DIO0..3) is depending on the length of the custom dataset. The setup: Clock (DIO4): Pulse-Mode, Div=5 (=20MHz; T=50ns), Counter=(2,2)(=5MHz) CounterInit=(0,300) Bus (DIO0..3): Custom-Mode, Div=5(20MHz;t=50ns), Counter=(autoset by custom pattern) CounterInit=(0,300) The delay I expected is 300*50ns=15us, but what I measure Clock(DIO4): measured: 15us --> result as expected Bus(DIO0..3): measured: 10us --> not as expected and it is strongly depending on the data-set length - why is that ? To match the delay with a dataset-length of 624, a init value of 924=300+624 is required: Bus (DIO0..3): Custom-Mode, Div=5(20MHz;t=50ns), Counter=(autoset by custom pattern) CounterInit=(0,924) Why this high initial counter value ?
  13. Okay, there is no way to start and stop single DIO channels independently whilst others are still running indefinitely ? Can you quickly comment to my above comment about the clock frequencies at the output: I saw it also in the SDK examples and think it is not correct how the frequency is given. In your above example (and also in SDK python-examples), it is said to generate a 10MHz clock by: dwf.FDwfDigitalOutDividerSet(hdwf, c_int(adc_clk), c_int(10)) dwf.FDwfDigitalOutCounterSet(hdwf, c_int(adc_clk), c_int(1), c_int(1)) But that is not correct - it generates a 5MHz clock because the counter always divides by 2 at a minimum: dwf.FDwfDigitalOutDividerSet(hdwf, c_int(adc_clk), c_int(10)) #divider generates a 10MHz outpiut clock dwf.FDwfDigitalOutCounterSet(hdwf, c_int(adc_clk), c_int(1), c_int(1)) #counter output is a 5MHz clock with 50% duty cycle and thus adc_clk is
  14. Hi @attila, the bus uses a proprietary protocol with 1 clock + 4 datalines to program a custom IC. The custom IC provides analog values at a pin, which are captured by an ADC. Once the custom IC receives command 0x0B it starts to provide analog values per rising and falling edge at the output - this is kind of a DDR but for analog values. Each analog value is sampled by the rising edges of the ADC (that is wha the ADC has a 10MHz clock). According to your example, the clock on DIO12 is typically 5MHz syncing the bus on DIO8..11. The ADC clock DIO13 is typically 10MHz and running at least 1ms (thats enough for ADC PLL lock) before the first DIO12 clock occurs. The data on DIO8..11 will be user-specific for the first 4-6 samples (in my example I just count 0x1, 0x2, 0x3) until 0x0B is there - but those data are occuring only once. Then 63 samples (127 ADC samples) cycles to provide analog values where data on DIO8..11 HAVE to be 0x0. The 64th sample MUST be 0x03 (this increases an internal counter to select the next memory cell). Then 63 samples where data on DIO8..11 HAVE to be 0x0. The 64th sample MUST be 0x03 (this increases an internal counter to select the next memory cell). Then 63 samples where data on DIO8..11 HAVE to be 0x0. The 64th sample MUST be 0x03 (this increases an internal counter to select the next memory cell). ... and so on ... this is repetitive until we have captured a user defined number of analog values. In you above example, how did you delay the DIO8..12 - just sending 0s ? This is what I am trying to implement currently - unfortunately I will loose ~5k samples from DigiDisco 32k data-memory, if I try to assemble the whole communication into one dataset ? Insert other media
  15. One more thing I cannot achieve yet is, that once the delayed signals are activated unblocked by dwf.FDwfDigitalIOOutputEnableSet(hdwf, c_int(0x0000)), I need to run a custom dataset for a specific time and only once. But this seems not to work, when unblocking the DIO output. Here is what I do: # blocking all signals except for clk dwf.FDwfDigitalIOOutputEnableSet(hdwf, c_int(0xFFDF)) #all DIOs blocked except for DIO5 #configuring all outputs DIO0..5 dwf.FDwfDigitalOutEnableSet(hdwf, c_int(pixcmd0), c_int(1)) # set to output dwf.FDwfDigitalOutTypeSet(hdwf, c_int(pixcmd0), DwfDigitalOutTypeCustom) # Custom type allows to send DataSet dwf.FDwfDigitalOutOutputSet(hdwf, c_int(pixcmd0), DwfDigitalOutOutputPushPull) # drive output load dwf.FDwfDigitalOutDividerSet(hdwf, c_int(pixcmd0), c_int(div_pixcmd)) # set divider ... and so on.... dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) #start the DIO device (non-blocked outputs only) time.sleep(1e-6) #wait some time to ensure the ADC PLL is locked dwf.FDwfDigitalOutRunSet(hdwf, c_double(nSamples/fpixclk)) #define time to run dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # run only once dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) #start the DIO device (non-blocked outputs only) dwf.FDwfDigitalIOOutputEnableSet(hdwf, 0x0000) #enable all other outputs To make clear what I want to achieve, I attached a (photoshopped) image: Here is what I achieve: The data on DIO0..4 are just starting arbitrarely, but I want them to start at 0x0, 0x1, 0x2 ... and so on