ozden.erdinc

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  1. Hello @[email protected], I created axi fifo and I used axi dma ipcore to write and read ddr3 memory in my microblaze design and I successed! Ican read and write PL side ddr3 memory. Also thanks for your helps .
  2. Thank you @JColvin. By the way How can I store my data in seven mig series ddr3 ip core. Can you suggest any idea? Or can I write custom fifo ip core with axi4 interface, after that I will connect with ddr3 ip core? Is that possible or not? Thank you.
  3. Hi @xc6lx45, I am working Zynq Ultrscale MpSoC+, I didn' t configure the PS DDR settings. Is DDR that you say belong to PS side , am I wrong?. I dont want to use PS side DDR. I want to use only PL side DDR. My mind is confuse. But I want to write and read data patetrint into the PL side DDR? Can you help me this issue? Thank you.
  4. Hi, I am working Ultrscale MpSOC+ and I added DDR4 which is provided from vivado but I did not recustoimize that's why I want to create my DDR4 IpCORE.Also I want to access DDR in PL part.
  5. Hello, I have issues with DDR4 ipcore design in PL part. Also I am using vivado 2019.2 version.I want to redesign and use DDR4 and I want to write and read huge data sets into the DDR4 in vivado as IPCORE but I could not find any resources about how can we create custom ddr4 ip core. Can you helo me about these issues as soon as possible? Thank you. Best Regards.
  6. Okey then I will create only constraint files to define the pins that I will use it. Thank you @BogdanVanca
  7. Hello @BogdanVanca Actually I want to use my board which I designed but I could not know the wheter board files are needed or not. I will use only the XC7A50T-2FGG484I chip. Are constraint files enough to load and use the my board?
  8. Hello, I have problem with board file for XC7A50T-2FGG484I in vivado 2015.4. I could not find anywhere board file to upload the vivado that family. Can you help me with this problem? Thank you.
  9. Okey No problem. I will look at the links, I hope they help me. Thank you.
  10. Hello, I am using Arty7 board and I am strugglling with DDR3 RAM in Microblaze. I added to my design UART core Mig7 series core. Also, I have data set to write the DDR3 RAM after writing operation I will read these data set. Unfortunately, I couldnt upload into the DDR3 ram that data set. How can handle with thise issue? Can you help me?
  11. I tried suggested design by using axi quad spi. It works,thanks for your help.
  12. Hi @jpeyron, Yes I am using Arty A7 board I saw that you gave me the link which is getting started with microblaze but unfortunately I want to design Spi interface. My axi quad spi will work as a slave and I selected 1 master 1 slave and I added DDR3 but I got critical warning also when I export these design to the SDK platfrom. I did not build my exist SPI code I got too many times .elf file error. So I am really dealing with SPI. Could you help me this issue especially about vivado part hardware design. Thanks for help. Best Regards
  13. Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.