ozden.erdinc

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About ozden.erdinc

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  1. Okey No problem. I will look at the links, I hope they help me. Thank you.
  2. ozden.erdinc

    Microblaze DDR RAM

    Hello, I am using Arty7 board and I am strugglling with DDR3 RAM in Microblaze. I added to my design UART core Mig7 series core. Also, I have data set to write the DDR3 RAM after writing operation I will read these data set. Unfortunately, I couldnt upload into the DDR3 ram that data set. How can handle with thise issue? Can you help me?
  3. I tried suggested design by using axi quad spi. It works,thanks for your help.
  4. Hi @jpeyron, Yes I am using Arty A7 board I saw that you gave me the link which is getting started with microblaze but unfortunately I want to design Spi interface. My axi quad spi will work as a slave and I selected 1 master 1 slave and I added DDR3 but I got critical warning also when I export these design to the SDK platfrom. I did not build my exist SPI code I got too many times .elf file error. So I am really dealing with SPI. Could you help me this issue especially about vivado part hardware design. Thanks for help. Best Regards
  5. ozden.erdinc

    Vivado AXI QUAD SPI

    Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.