Arty7_Lover

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  1. Thanks, a lot. Your kind and easy answer is greatly helpful to me.
  2. I want to select a arty7 board in vitis Create Application Project . or I use arty 7 board in vitis program. Could you answer me, please ?
  3. how much is delay time of bufio gate in zynq z7-20 ? I want to use bufio delay time to use (* io_buffer_type ="bufio" *). How much is time bufio delay time ? Can I increase bufio delay time ? if not so, I want to use another more sufficient delay time of other gate ? Could you recommend it?
  4. Can Axi-lite connect with AXI4 slave bus directly?
  5. I have synthesized zynq block well , but implementation removes bram. My picture is as follows. Implementation is made after runing block automation. Could you explain it? AXI_Traffic_Generator.srcs.zip
  6. Thank you for your answer. I have solved my problem with FS_CLK not to be worked. this problem might be bitstream file not to be exported. (maybe not updated)
  7. Can I ask a question of Rule #1? I have learned Rule #1 in school, But I think that I could use two edges because they can support setup time and hold time not to occur metastable stable. I think that Just one edge have not sufficient setup time or hold time because routing delay and combination delay is too short. Is My thought wrong?
  8. I have solved my problem due to your help. I have took a mistake not to connect Led output ports. Thanks.
  9. Hi problems : If I press btn0 or btn1 , then led1 or led0 should be on. But, led1 or led0 would turn off. I added module IP to defaults preset Arty z7-20 . I had a problem not to get FS_CLK from your directions. How can I get or enable FS_CLK from defaults settings? LED_out.v
  10. I have solved my problems due to your help and kind answers. Thanks.
  11. My Arty z7-20 have micron 7EP47 D9SHD. I should have a datasheet of it or part number because I have to know about it. I can not find 7EP47 in web. Is it MT41J256M16 RE-125? And If I press Preset defaults to make a Arty z7-20 project in Vivado to be installed Arty z7-20, I see MT41J128M8JP-125. It is 512Mb. ( Arty z7-20 have 4Gb) So , I think that there is some problems in defaults memory Parts Selections. I want to know which parts selection of DDR. Zedboard is MTJ128M16HA-15E If I select preset to Zedboard. I want to have wright memory (perhaps,MT41J256M16 RE-125 and configuration information in menu) to preset Arty z7-20.
  12. Which DDR memory can I select in Zynq ? In Arty z7-20, DDR memory is 512MBytes, 16bit, 1050 Mbps. In Vivado IPI zynq, Which parts can I select in fictures (file to be attached )
  13. Hi,everyone I add just zynq IP to block ( Arty z7-20) and lauch sdk with hello world. But I meet error message above. Could you give me a solution ? design_1.zip