hiroowada

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About hiroowada

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  1. Hi. It went well. Your advice gave me a step into the world of FPGA. Thank you.
  2. I purchased Nexys A7-100T. My PC is Windows 10. I tried to run "Getting Started with Vivado" on the Digilent home page, but I can not take steps. I installed “Vivado Design Suite-HLx Editions-2016.2 Full Product Installation” on my PC according to the “Installing Vivado and Digilent Board Files” tutorial on the Digilent home page. I installed Digilent Board Files as instructed. Next, I tried to execute "Getting Started with Vivado" on the homepage of Digilent, but I can not take steps. I do not know where in my procedure is wrong, so I will write as much as possible. Launched Vivado HLx and created a new project. I entered a project name in the "Project Name" dialog. I checked "Create project subdire". In the "Project Type" dialog, select "RTL Project" and check "Do not specity sources at this time". Next, I selected "Nexys-A7-100T" in the "Default Part" dialog. Then I pressed the "Finish" button in the "New Project Summary" dialog. Next, "6 Adding a Constraint File" of "Getting Started with Vivado" I tried to add Constraint File as described in . I downloaded Nexys-A7-100T-Master.xdc from GitHub. I clicked "Add Sources" in Project Manager. I have selected "Add or create constraints" in the AddSources dialog. Next, I clicked "Add Files" button in "Add or Create Constraints" dialog and selected Nexys-A7-100T-Master.xdc. And I pressed the "Finish" button. Next I double-clicked Nexys-A7-100T-Master.xdc to open it. I did not find "sysclk" at the top of the XDC file. When I searched for "clk" in the xdc file, I found the code as shown below. Should I fix it as follows? In addition, when I searched for "led [0]" in the xdc file, there was the following code. Should I fix it as follows? Please give me some advice. Thank you
  3. Thank you for your polite advice. The software worked well. Thank you.
  4. I am a beginner of FPGA. I purchased Nexys A7-100T. I installed Vivado and Digilent Board Files.(My PC's OS is Windows 10.) I installed the version supported by the following document. Digilent Documentation : Reference : Programmable Logic : Nexys A7 : Tutorials : Installing Vivado and Digilent Board Files The software I installed is “Vivado Design Suite - HLx Editions - 2018.2 Full Product Installation”. I installed Digilent Board Files as instructed. Next, I tried to execute what is written in the Digilent Documentation vivado Getting Started with Vivado. The document first says "This guide was created using Vivado 2016.4." So, the version written in "Getting Started with Vivado" is different from the version I installed. I first pressed the "Create New Project" button. A dialog box titled "Project Configuration" was displayed, so I set the Project name and pressed the "Next" button. Then a dialog box titled "Add / Remove Files-Add / remove C-based source files (design specification)" will be displayed. The description for this dialog box was not found in the document. How should I do? Click "Next>" button in this dialog and then "Add / Remove Files" A dialog titled Add / remove C-based testbench files (design test) is displayed. How should I do? Next, the dialog box "Create Vivado HLS solution for selected technology" will be displayed. How should I do? Please give me some advice.