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  1. Hi @jpeyron If I leave JP5 set to JTAG after programming the FPGA, the error presents itself. The strange thing is that when I place the JP5 jumper across the QSPI pins after programming the FPGA, the SDK also throws an error about some AP memory overflow something or other. All pins left floating and the application runs without issue😖 Not sure what what you're asking for here: If you're asking where I found this suggestion on the web - I didn't. I was getting different errors depending on whether I had JP5 set to QSPI or JTAG after the programming the FPGA so I just left all pins on JP5 floating to see what would happen 🤔. I know it sounds hokey but it definitely works for some reason...
  2. Hi @jpeyron, Yes, I confirmed the following: I stumbled onto a solution whereby removing the JTAG jumper (thereby leaving all pins on JP5 floating) after step 11.2 allows the SDK to recognize the Zybo board and execute the hello world example. Maybe this is a bug in the version of Vivado I am using (2017.1) or combination of this version running on Windows 10 Enterprise or maybe this is just an undocumented understanding that the jumper has to be removed after programming of which I am uninformed. Does this make any sense to you? In any case, it allows me to get up and running now though I am a little concerned about what ramifications may follow if I continue programming the board in this manner using more customized programs and bit files.
  3. Hi @jpeyron Adept 2 does recognize my Zybo board so I went ahead and re-generated the BSP - this did not aid in getting the SDK to recognize my specific board (same error I posted previously). I then deleted the SDK folder from the project directory and re-exported the hardware from Vivado including the bistream - this also did not resolve the error. At your request I have attached here a screen shot of the SDK gui with the hardware platform expanded. Any other thoughts? I will go ahead and post the "no targets found" error in the Xilinx forum as you suggested. Thanks again for your assistance.
  4. Hi @jpeyron I'm inching closer. Reinstalling Vivado 2017.1 with the 2015 VC++ libraries pre-installed and the VC++ check disabled seemed to do the trick. So I'm still stuck on step 11.3 but the error now appears to be associated with Uart communication. JP5 is configured for JTAG. I've included a screenshot of the launch error here for your reference. I'm able to establish communication to the ZYBO with the SDK terminal but its running the demo image. I can't seem to get this hello world program loaded. Could it be as simple as a string formatting issue in the launch script? From the error message, it appears that the SDK is seeing an available target but just not of the format it is filtering on?
  5. Thanks for your reply Jon. I installed Vivado 2017.1 and this got me past step 9.3. Unfortunately, Vivado 2017's 2015 VC++ redistributable package dependency does not appear to install properly on Windows 10 enterprise. DLLs seem to be missing everywhere and when I execute step 11.3 I get an error about shsmp64.dll missing. I had to hack the Vivado 2017 install to skip the VC++ check just so the Vivado suite would open but this does not fix the underlying problem of the misplaced DLLs. Are you running Vivado 2017 on Windows 10 by chance?
  6. I'm getting spun up on the ZYBO Z7-20 and I am having difficulty executing step 9.3 in the "Getting Started with Zynq" tutorial here. When I get to this step and select "Hello World" in the SDK's New Project templates GUI, the GUI says "This application requires a Uart IP in the hardware" and will not allow me to finish with the hello world project. I do notice that the USBIND_0 port is mysteriously missing from my instantiation of the ZYNC7 Processing System block after executing "Run Block Automation" in step 3.2 I am running on Vivado 2015.1 and as far as I can tell I have properly installed the board files from the github repository; the project summary indicates the correct board and the ZYBO LEDs are blinking and the switches control the LEDs as programmed in the steps preceding step 9. Any thoughts on what is going awry here?
  7. Hi, I'm new to the digital discovery and Waveforms. I am trying to figure out how to setup an external trigger with the digital pattern generator and the only trigger configurations available in the "Patterns" window are none, logic, logic detector, and manual. It isn't clear to me how to specify which pin the digital discovery should expect to see my external trigger. My research of all the documentation on the digital discovery and Waveforms has lead me astray. The Logic Analyzer window offers more configuration options but it isn't clear to me that these options carry over to the pattern generation utility. Can someone tell me how to configure the digital pattern generator for external triggering?