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  1. I've made some progress on this since I last posted. I based my original custom logic design on the OOB user demo which had a component to read the temperature from the XADC to give to the MIG. When I deleted that block (and therefore, had to delete the MIG) I was able to get things to work. My new confusion moving forward is getting both the custom vhdl and the micoblaze to talk to the DDR2 at the same time. Right now I have two separate MIG instantiations, but whenever I try to leave both instantiations uncommented (but even when I leave the pins of one connected to "open") I get tons of errors. I of course expect some issues because I removed the connection to the XADC temperature sensor and just set MIG input for temperature to a fixed value as a test. However, I can't seem to get the code to implement. My question is, should I now try to debug my errors in the instantiation, or should I try to redesign only using one MIG block and changing which interface (microblaze or custom vldl) connects to it? Is it even possible to have two MIG blocks for the same chip in a project? Thanks, Daniel EDIT: It seems like I am going to need two separate MIG instances because the one that should talk to microblaze needs an AXI interface while the one I use for VHDL has a normal interface. Any suggestions on how I might do that?
  2. Ah, thank you @kwilber. That explains why the XADC error shows up at all, but I'm guessing that the XADC part may be a red herring on what is actually going wrong? I seem to get this error even when I completely disable the MIG ip core that I use in my custom VHDL code, but the error goes away when I comment out the port map for either my custom code or microblaze completely.
  3. Hi, I'm trying to create a project that uses custom HDL code to write to the DDR2 memory on my nexys 4 ddr, and then ultimately uses microblaze to read the memory out over UART. As an intermediate step, I created a vhdl "wrapper" to connect microblaze to ram and instantiate my custom vhdl. At first I want to leave the signals from the custom VHDL that go to ram open/disconnected. My plan was to later add a conditional logic statement that decides which is connected. When I try to leave the pins to memory "open", or even connected to junk placeholder signals I created, I get an implementation error: This doesn't make any sense to me, especially as I am not trying to use the XADC anywhere in the project. I saw this article about leaving pins open, but I believe I followed the solution they have listed but still get the error. I've attached the project folder for this in case anyone may be able to take a look. Since the file is too large to attach, it is at this google drive link. Thank you, Daniel
  4. Hi Jon, That makes sense, I guess I shouldn't expect consistent results out of undocumented behaviour. Thanks again for all your help. I think that solves my problem, though in the process of solving this one, another problem came up. I guess thats a topic for another thread... Thanks, Daniel
  5. Hi Jon, Thank you so much! Your project seems to work fine on my computer, even after I regenerated the IP to update them and regenerated the bitstream. I'm trying to figure out what the difference could be between the projects, and ideally figure out what is wrong without just starting over. The only difference I can see in our block designs is that yours has an axi_smc block to connect to MIG whereas mine connects through the microblaze_axi. Could that be the difference, and is there a way to fix that? EDIT: That was the difference. I redid the tutorial from a new project making sure to follow everything exactly, and It now generates the same design that you got. Any idea what I did wrong before? Also, another thing that changing this brought up, is now pushing the cpu-reset button doesn't seem to reset the CPU. Any idea on why that would change and how to fix that? Thanks, Daniel
  6. Hi Jon, Thanks again for your help. Is it necessary to include the QSPI in this program? I was planning on loading the program from my computer over usb when running it, and have no need for persistent memory, just ram. I tried adding the DDR2 connection from the board port to my design, and reverified the design, then regenerated the outputs, rewrote the bitstream, and now when I try to export the hardware to the SDK to test I get the following common error: I've tried all the suggestions to solve it I've found on the Xilinx forums. Any ideas to go forward? Thanks, Daniel EDIT: Generating the IP for microblaze as "Out of context per IP" as opposed to "Global" seemed to fix the problem. I'm not sure what that did though. I still have the issue where no data is sent through UART if the linker settings are set to mig.
  7. Hi Jon, Thanks for the reply and the welcome! I was a bit confused by step 10 because the 100 MHz system clock was already connected (I think from running connection automation in the step before), so I disconnected it by deleting the entire line for the system clock, manually connecting it to the 200MHz clock, and then re-running connection automation to fix all the other components that used the 100MHz sys_clock. I believe I was careful to copy the settings from the image in the tutorial, but I'm not 100% sure and I don't know how to check those settings now. If I remember correctly, I set local memory to 32K and Cache to 16K. I've attached the block design. Out of curiosity, is there any special feature to block designs that can't be done using the ip catalogue? Is everything in a block design eventually combined down to sources in the same way that they could be added manually? I'm having trouble understanding when to use the block design, and when to directly add sources (especially when trying to mix microblaze/IP with my own vhdl). Thanks again, Daniel EDIT: One thing I noticed after posting this is that in the "Board" folder it suggests that the DDR2 is not connected, despite it showing the connection on the right side of the diagram. The ddr2 also seems to be connected when I look at the synthesis IO planning window. Could that be related?
  8. Hi, I am trying to follow the Nexys 4 DDR getting started with microblaze tutorial and I'm having trouble completing step 20. I believe I followed step 11 correctly, but when I get to step 20, if I set the memory region to mig_7series_0_memaddr (I have no option for just mig_7series_0, as specified in the tutorial), nothing transfers over UART when I run the program on the FPGA. If, however, I leave the default memory region (microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem), UART seems to work fine and I get "Hello World" printed. Can someone help me understand the meaning of this setting, and will leaving it set to microblaze_0_local_memory... cause any problem in this project/future development? Ideally, I would like to build up to projects that use the capability of the DDR2 memory. Thanks, Daniel