SmashedTransistors

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About SmashedTransistors

  • Rank
    Newbie
  • Birthday 07/06/1969

Profile Information

  • Gender
    Male
  • Location
    Issy les moulineaux FRANCE
  • Interests
    Sound Synthesis using the Axoloti and maybe the Basys3
  1. Thanks Zygot, I use an Axoloti board and C code my algorithm to test them and evaluate the different options (quantification, polynomial waveshaping vs sine in RAM etc...). It really helps to know how it should sound. I decomposed the pipeline in smaller entities. The architecture of each component already include fine pipelining. I try to track the clock delays involved by each architecture so that the result will be consistent. With all the elements i plan, i would say that the pipeline will consist in 20 to 30 registers. I think it will be possible to add extra pipeline registers between the components if the internal ones are not enough. Or should i implement different architectures for the same entities with different pipelining ?
  2. Hello, I am really enjoying my Basys3. I already VHDL coded/simulated/tested a little SPI and a little I2S controller (connected to a AdaFruit DAC, but i will try/compare it with the I2S2 soon). Thanks to many threads on this forum (double flop...), clock domains were not such a big problem I am designing a formant/phase modulation synthesizer. It will be based on 1024 "operators" (oscillators with phase modulation, phase hard sync and many other delicacies). I use a dual port BRAM connected to a SPI controller for input parameters (frequencies and gains) and another set of BRAM for state variables (for example the phase of each operator). I am designing the "operator" processor as a pipeline (so that it will calculate the equivalent of 1024 oscillators at the I2S 96kHz sample rate). I'd like to have a rule of thumb for the granularity of the pipeline for a targeted clock frequency. (for example the number of adders or multiplexers between two pipeline registers at 100MHz or 200MHz) I browsed many documents and i did not find such a rule of thumb... thus i have a tendency to over-pipeline my design... and it makes it quite confusing. Is there some Xilinx document that gives some advice/good practice ?
  3. Thanks @OvidiuD, I'll take one step after another and the forums are quite a good source of knowledge. So far, I plan to start with very basic schemes in order to understand how Vivado works. Then I will work on communicating with the Axoloti through SPI. Best regards
  4. Hello from Paris France, I've just received a nice Basys3 and Pmod I2S2. I plan to use these for sound synthesis. I'm quite confident with DSP and synthesis stuff as I experiment my algorithms on the Axoloti (an Arm based plateform). I plan to use the Artix 7 as a sidekick for the Axoloti. It will be dedicated to a rather simple, yet usually CPU intensive, algorithm such as Additive Synthesis or Formantic Waveform Synthesis. Well, that's my long run project. For the moment, I'm back to FPGA/VHDL 101 and blinking leds. I've already browsed the Forums and i want to thank everybody for their insight :D