PoojaN

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  1. Hi @jpeyron Thank You!! There was a problem with the cord. I don't know why that would happen though, as I have been using this cord for a long time and it works with the other boards. Cheers!! -P
  2. @jpeyron I tried to use this file with CMOD A7. I was able to generate the bitstream with this project, but when i tried to upload it to the CMOD, i got the following error Did I do anything wrong? -P
  3. PoojaN

    Custom IP

    @D@n Thank you for the detailed explanation! I wanted to learn about the IP cores, so I thought that I would start with something as simple as blinking an LED. But looking at how working with IP cores is, I think it would be better if I don't take up on such a herculean task right now. I will read up all the material that you have posted. Thank You! -P
  4. PoojaN

    Custom IP

    Hi @D@n Thanks for your reply. I will read through all the material that you have posted. But personally I think, shouldn't this be easy and user friendly rather than being so complicated? -P
  5. PoojaN

    Custom IP

    Hi! I am using Arty A7 board with Vivado 2019.1. I wanted to get familiar with IP Integrator. I followed all the tutorials available for it. Now I want to interface RTL and IP blocks, so I wrote a simple Verilog code for an AND gate using buttons and LEDs and created a block of the code by 'Add Module to Block Design'. It looks like this, Now I wanted to integrate it with the AXI GPIO block, but whenever I try to make connections, Vivado says 'No Ports found'. Am I doing it wrong? How can I go about it any further? Or can anyone tell me just how to glow a few LEDs using buttons with only IP and not code. -P
  6. PoojaN

    Arty A7 and MIG

    @jpeyron @D@n Thanks a lot for the help. I figured out how to use the MIG interface. P
  7. PoojaN

    Arty A7 and MIG

    Hi @jpeyron Thanks for the quick reply. I have already completed the steps till System Signals Selection. I have a problem regarding Systems Signals Selection. Also could you please tell me how to directly use the mig.prj file in Vivado? Thankyou
  8. PoojaN

    Arty A7 and MIG

    While selecting the Memory Part while configuring the MIG, I realized that the memory type mentioned in the Arty A7 documentation, MT41K128MJT-125 was not listed. Would the available part, MT41K128M16XX-15E work instead as mentioned in this Digilent thread https://forum.digilentinc.com/topic/17916-genesys-2-ddr-constraints/#comment-45996 ? Also what banks or I/O am I supposed to enter for these constraints? Thanks
  9. PoojaN

    UCF to XDC

    I just got an answer for this question. "There are no Schmitt trigger inputs in 7-series FPGAs." @jpeyronThank You for the quick help!!
  10. PoojaN

    UCF to XDC

    I got the following error when I used this command in the XDC [Netlist 29-69] Cannot set property 'SCHMITT_TRIGGER', because the property does not exist for objects of type 'port'. ["C:/Projects/raccer_board_1/raccer_board_1.srcs/constrs_1/new/raccer.xdc":11].
  11. PoojaN

    UCF to XDC

    Yes I tried that, but gives me the following error [Netlist 29-69] Cannot set property ' set_property SCHMITT_TRIGGER TRUE [get_ports {JA[0]}]', because the property does not exist for objects of type 'port'. ["C:/Projects/raccer_board_1/raccer_board_1.srcs/constrs_1/new/raccer.xdc":11]. I also tried changing the names and trying out all possible permutations and combinations to not get an error.
  12. PoojaN

    UCF to XDC

    I had a written a code for one of my boards a few years back using ISE. Now I want to transfer it to Vivado. I had used the following line in the UCF file before,\ NET "INPUT_1" LOC = "P6" | IOSTANDARD = LVCMOS33 | SCHMITT_TRIGGER ; I changed it to xdc in the following way, set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {INPUT_1}], but I don't understand where can I enter the SCHMITT_TRIGGER IOSTANDARD? Can anyone help me with this?
  13. PoojaN

    Make a new Board

    So where do I start with this, because the Configuration User guide is pretty overwhelming.
  14. PoojaN

    Make a new Board

    Hi @jpeyron No I am not looking to route the DDR3, but that is helpful in either way. My problem was, if I make my own board, how will I interface Flash memory with the FPGA so that I can store my own code. I would need a flash circuitry as well as there must be some programming involved for when to pull the CS low or high. Thanks, P
  15. PoojaN

    Make a new Board

    I have been doing projects on Arty A7 board, and I wanted to try to make my own development board. But I don't understand how to interface memory with the chip. Can anyone help me with this?